Novel nonlinearity minimized time-to-digital converters with digital calibration technique

Latha, P.; Sivakumar, R.; Rao, Y. V. Ramana; Ko, Seok‐Bum

doi:10.1007/s10470-022-02065-4

Cited by 1 publication

(1 citation statement)

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“…The external PLL is a high-precision clock (248.88 MHz) close to the router's clock frequency, and the difference between its clock cycle and the router's clock cycle is the resolution of clock synchronization. The resolution of clock synchronization cannot be enhanced infinitely, since a higher resolution needs a larger amplification factor A for the phase difference, which may cause the metastable state of the D flip-flop [34]. According to the clock IP core MMCM of the Xilinx 7 series FPGA, the highest dynamic phase-shift precision is 1/56 of the internal VCO period.…”

Section: The Implementation Of Ddmtd (1) Phase Discrimination Of Mast...mentioning

confidence: 99%

Research on Clock Synchronization of Data Acquisition Based on NoC

Meng,

Xu,

Liao

2024

Applied Sciences

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Data acquisition based on network-on-chip (NoC) technology is a high-sampling-rate data acquisition scheme using low-sampling-rate analog–digital conversion (ADC) chips. It has the characteristics of multi-task parallel communication, being global asynchronous, local synchronous clock distribution, high throughput, low transmission latency, and strong scalability. High-speed data acquisition is realized through the combination of an on-chip network and time-interleaved data acquisition technology. In the time-interleaved sampling technique, the precision of clock synchronization directly affects the precision of sampling. Based on the proposed NOC data acquisition scheme, an improved White Rabbit clock synchronization protocol is applied to high-speed data acquisition to achieve high-precision synchronization of multi-channel time-interleaved sampling clocks. Firstly, the offset of the master clock and slave clock is determined by the PTP protocol, and the offset is corrected to achieve rough synchronization between the master clock and slave clock. Secondly, a digital dual-mixer time difference (DDMTD) is used to measure the phases of the master and slave clocks. After that, the phase of the slave clock is corrected through the dynamic phase-shift function of the clock’s phase-locked loop (PLL). Finally, according to the simulation results in Modelsim, the average absolute error of a TI-ADC sampling clock can be less than 20 ps.

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Section: The Implementation Of Ddmtd (1) Phase Discrimination Of Mast...mentioning

confidence: 99%