A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR

Leibowitz, Brian; Kizer, J.; Lee, Haechang; Chen, F.; Ho, A.; Jeeradit, Metha; Bansal, Akash; Greer, Thomas H.; Li, S.; Farjad-Rad, R.; Stonecypher, W.F.; Frans, Yohan; Daly, Barry; Heaton, Fred; Gariepp, B.W.; Werner, C.; Nguyễn, Nam Thành; Stojanović, Vladimir; Zerbe, J.

doi:10.1109/isscc.2007.373377

Cited by 47 publications

(14 citation statements)

References 6 publications

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“…Since it increases the relative strength of the high-frequency components of the transmitted signals, crosstalk is also reduced [8]. Near-end channel equalisation is often implemented using finite impulse [9] 130 nm −12 dB (26″ FR4) 5 -1-tap -Balan et al [10] 130 nm −(40″ FR4) 6.4 2-tap 4-tap t L Wong et al [11] 9 0 n m −6.2 dB (10″ SMA) 6.0 -2-tap 10 −12 Park et al [12] 9 0 n m −12 dB (16″ Tyco) 7.0 -2-tap 10 −13 Leibowitz et al [13] 9 0n m −(18″ BP) −7.5 -10-tap 10 −12 Bulzacchelli et al [14] 9 0n m −33 dB (16″ Legacy BP) 10 4-tap 5-tap 10 −12 Hidaka et al [15] 9 0 n m −25.4 dB (29″ FR4) 10 response (FIR) filters that introduce zeros to offset the effect of the poles of the channels [45,46]. For example, the first-order pre-emphasis FIR filter shown in Fig.…”

Section: Near-end Channel Equalisationmentioning

confidence: 99%

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Design techniques for decision feedback equalisation of multi‐giga‐bit‐per‐second serial data links: a state‐of‐the‐art review

Yuan

Al-Taee

et al. 2014

IET Circuits, Devices & Systems

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This study provides a comprehensive review of decision feedback equalisation (DFE) for multi-giga-bit-per-second (Gbps) data links. The state-of-the-art of DFE for multi-Gbps serial links reported in the past decade are compiled and presented. The imperfection of wire channels, in particular, finite bandwidth, reflection and cross-talk and their impact on data transmission are investigated. The fundamentals of both near-end and far-end channel equalisation to combat the effect of the imperfection of wire channels at high frequencies are explored. A detailed examination of the principle, configuration, operation and limitation of DFE is followed. Design challenges encountered in design of DFE for multi-Gbps data links including timing constraints, sampling, error propagation, arithmetic operation, highly dispersive channels, power consumption and techniques and circuit implementations that address these challenges are studied. The need for adaptive DFE and the principles of adaptive DFE are investigated. Finally, the performance of various adaptive DFEs is examined and their pros and cons are compared.

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Section: Near-end Channel Equalisationmentioning

confidence: 99%

“…As the output of the summer directly Fig. 8 Clocked re-generative sense amplifier as slicer [13,15,61,62] www.ietdl.org feeds the slicer, a large output voltage of the summer is essential to minimise slicer error. Increasing the dimension of the input transistors improves output voltage swing, it, however, also reduces the speed.…”

Section: Arithmetic Operationmentioning

confidence: 99%

Design techniques for decision feedback equalisation of multi‐giga‐bit‐per‐second serial data links: a state‐of‐the‐art review

Yuan

Al-Taee

et al. 2014

IET Circuits, Devices & Systems

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show abstract

“…All need to be completed within one UI for tap-1. Loop-unrolling has been proven to be an effective technique in meeting the timing constraint of the tap-1 of DFE [19,[58][59][60]. High-order loop-unrolling also emerged when data rate exceeds 10 Gb/s, however, at the cost of high silicon consumption [10,11,61].…”

Section: Channel Equalizationmentioning

confidence: 99%

Design Techniques for High-Speed I/Os: Challenges and Opportunities

Yuan¹

2014

J Elec Electron Syst

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“…The feedforward path, however, was realized by a sample-and-hold (S/H) circuit which may generate feedthrough noise. In [10], either zero-offset edge sample or non-zero-offset edge sample is selected as the input of the CDR loop filter based on three consecutive data samples to avoid the bi-modal jitter distribution of the CDR output. Because the current data sample has to be determined before selecting the edge sample, however, the timing margin cannot be relaxed.…”

Section: Introductionmentioning

confidence: 99%

Data and edge decision feedback equalizer with >1.0-UI timing margin for both data and edge samples

Bae

Yoo

2014

IEICE Electron. Express

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A 3-Gbps decision feedback equalizer (DFE) compensating for data and edge inter-symbol interference (ISI) is presented. A speculative architecture is employed to relieve the timing burden on the feedback signal for the DFE wherein the ISI of edge sample is compensated by speculating the DFE based on two-UI earlier data sample. Thereby, the timing margins of the DFE for data and edge ISI compensation are ensured to be larger than 1.0-UI. The proposed DFE has been implemented in a 0.13-µm CMOS technology together with a clock and data recovery (CDR) circuit. The DFE and CDR circuits occupy 0.28-mm 2 active area and the DFE consumes 18-mW from a 1.2-V supply. The RMS jitter of the recovered clock is improved from 15.6-ps to 11.9-ps by the proposed edge ISI compensating DFE.

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A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR

Cited by 47 publications

References 6 publications

Design techniques for decision feedback equalisation of multi‐giga‐bit‐per‐second serial data links: a state‐of‐the‐art review

Design techniques for decision feedback equalisation of multi‐giga‐bit‐per‐second serial data links: a state‐of‐the‐art review

Design Techniques for High-Speed I/Os: Challenges and Opportunities

Data and edge decision feedback equalizer with >1.0-UI timing margin for both data and edge samples

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