A 6bit, 7mW, 700MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation

Abstract

A 6-bit, 7 mW, 700 MS/s subranging ADC using Capacitive DAC (CDAC) and gate-weighted interpolation fabricated in 90 nm CMOS technology is demonstrated. CDACs are used as a reference selection circuit instead of resistive DACs (RDAC) for reducing settling time and power dissipation. A gate-weighted interpolation scheme is also incorporated to the comparators, to reduce the circuit components, power dissipation and mismatch of conversion stages. By virtue of recent technology scaling, an interpolation can be realized in the saturation region with small error. A digital offset calibration technique using capacitor reduces comparator's offset voltage from 10 mV to 1.5 mV per sigma. Experimental results show that the proposed ADC achieves a SNDR of 34 dB with calibration and FoM is 250 fJ/conv., which is very attractive as an embedded IP for low power SoCs.

A 1-GHz, 7-mW, 8-Bit Subranging ADC without Resistor Ladder Using Built-In Threshold Calibration

“…The challenge in reference voltage generation using a CDAC is the gain variation of the CDAC. It has been reported that a gain variation of 15% degenerates the effect number of bit (ENOB) by 0.5 bit [16]. In this study, the ADC generated voltages corresponding to the top and bottom of the FADC input range by the CDAC, and the reference voltages for the FADC were generated by interpolating the top and bottom voltages.…”

A 6-Bit 20 GS/s Time-Interleaved Two-Step Flash ADC in 40 nm CMOS

“…On the other hand, single-channel two-step flash ADCs have often been utilized to maximize the aforementioned advantages of the flash and SAR ADCs [15][16][17][18][19][20][21]. However, it was previously reported that the two-step flash ADCs have drawbacks, which are as follows: (1) settling time required to select the reference voltage ranges for the fine ADC (FADC) [15][16][17]; (2) large input capacitance and offset calibration complexity due to the full flash hardware in the FADC [18][19][20]; (3) bandwidth mismatch due to an additional input sampler [21]. Because of these limitations, SAR and flash architectures have been preferred over the two-step flash architecture as a sub-ADC for the TI ADC.…”