A 6-bit, 1-GS/s, 9.9-mW, Interpolated Subranging ADC in 65-nm CMOS

Danjo, Takumi; Yoshioka, Masato; Isogai, Masayuki; Hoshino, Masanori; Tsukamoto, Sanroku

doi:10.1109/jssc.2013.2297416

Cited by 11 publications

(1 citation statement)

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“…Some of them are high power consumption and large chip area. Especially, due to increasing resolution of fully parallel A/D Converter, input capacitance of this system, chip area and power consumption become larger [7][8][9][10][11].…”

Section: Introductionmentioning

confidence: 99%

Design of A 5-Bit Fully Parallel Analog to Digital Converter Using Common Gate Differrential Mos Pair-Based Comparator

Aytar

2015

Journal of Electrical Engineering

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This paper presents a novel comparator structure based on the common gate differential MOS pair. The proposed comparator has been applied to fully parallel analog to digital converter (A/D converter). Furthermore, this article presents 5 bit fully parallel A/D Converter design using the cadence IC5141 design platform and NCSU(North Carolina State University) design kit with 0.18 µm CMOS technology library. The proposed fully parallel A/D converter consist of resistor array block, comparator block, 1-n decoder block and programmable logic array. The 1-n decoder block includes latch block and thermometer code circuit that is implemented using transmission gate based multiplexer circuit. Thus, sampling frequency and analog bandwidth are increased. The INL and DNL of the proposed fully parallel A/D converter are ( 0/ + 0.63 ) LSB and ( −0.26/ + 0.31 ) LSB at a sampling frequency of 5 GS/s with an input signal of 50 MHz, respectively. The proposed fully parallel A/D Converter consumes 340 mW from 1.8 V supply.

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