A 69-mW 10-bit 80-MSample/s pipelined CMOS ADC

Min, Byung-Jun; Kim, P.; Bowman, F.W.; Boisvert, D.M.; Aude, A.

doi:10.1109/jssc.2003.819166

Cited by 191 publications

(18 citation statements)

References 8 publications

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“…A decision is also made after a small delay (immediately after the SAH opamp enters the linear settling region) according to the SAH output during this phase. This is the early comparison technique described elsewhere [16]. In phase three, the input signal is sampled on capacitor set one and the capacitors C 1 ', C 4 ', C F1 ' and C F2 ' of capacitor set two are used to sample the references.…”

Section: Proposed Adc Architecturesmentioning

confidence: 99%

A Capacitor Mismatch Error Cancelation Technique for High-Speed High-Resolution Pipeline ADC

Park

Lee²

2014

IEIE Transactions on Smart Processing and Computing

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An accurate gain-of-two amplifier, which successfully reduces the capacitor mismatch error is proposed. This amplifier has similar circuit complexity and linearity improvement to the capacitor error-averaging technique, but operates with two clock phases just like the conventional pipeline stage. This makes it suitable for high-speed, high-resolution analog-to-digital converters (ADCs). Two ADC architectures employing the proposed accurate gain-of-two amplifier are also presented. The simulation results show that the proposed ADCs can achieve 15-bit linearity with 8-bit capacitor matching.Keywords: Pipeline ADC, Calibration, Capacitor error-averaging, Spurious free dynamic range(SFDR), Signal to noise and distortion ratio(SNDR), Effective number of bit(ENOB).

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Section: Proposed Adc Architecturesmentioning

confidence: 99%

A Capacitor Mismatch Error Cancelation Technique for High-Speed High-Resolution Pipeline ADC

Park

Lee²

2014

IEIE Transactions on Smart Processing and Computing

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“…To ease opamp design, lower resolution per stage is preferred [3]. The residue voltage after amplification maybe out of range for the next stage input due to the comparator offset if a 2-bit/stage is used.…”

Section: A 15-bit/stage Topologymentioning

confidence: 99%

“…For noise budget analysis, the input-referred thermal noise of the system is equal to the quantization noise defined in Equation (3). The quantization noise is (280µV rms ) 2 when differential peak-to-peak signal amplitude is 1V.…”

Section: B Opamp Specificationsmentioning

confidence: 99%

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Systematic design of 10-bit 50MS/s pipelined ADC

Zhu

Balagopal

Saxena

2013

2013 IEEE Workshop on Microelectronics and Electron Devices (WMED)

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Abstract-A systematical design analysis of a 10-bit 50MS/s pipelined ADC is presented. With an opamp-sharing technique, the power consumption is reduced drastically. Simulated in a 130-nm CMOS process, it achieves a 58.9dB signal-to-noise ratio (SNR), a 9.3 effective number of bits (ENOB), 64dB spurious free dynamic range (SFDR) with a sinusoid input of 4.858-MHz 1-Vpp at 50MS/s, and consumes less than 24 mW from a 1.2-V supply.

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“…The block diagram of a pipeline ADC with operational amplifier (opamp) sharing techniques [9] is shown in Figure 1. Due to the sharing of opamps, each block in Figure 1 implements two pipeline stages of the ADC.…”

Section: Proposed Reconfigurable Adc Architecturementioning

confidence: 99%

A Reconfigurable ADC Circuit with Online-Testing Capability and Enhanced Fault Tolerance

Gao

Wang

2009

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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This paper investigates techniques to minimize process-variation induced performance degradation in pipeline ADCs via circuit reconfiguration. By taking advantage of the modularity existing in pipeline ADC circuits, this work introduces a configurable switch network that makes it possible to move more accurate pipeline circuits to the preceding stages along the signal processing path. The reconfiguration feature also adds online testing capabilities and enhances fault-tolerance of pipeline ADCs. An implementation of reconfigurable 10-bit 1.5-bit per stage pipeline ADC circuit is presented. Circuit simulation shows both improved circuit performance and fault tolerance are achieved by circuit reconfiguration. 1

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A 69-mW 10-bit 80-MSample/s pipelined CMOS ADC

Cited by 191 publications

References 8 publications

A Capacitor Mismatch Error Cancelation Technique for High-Speed High-Resolution Pipeline ADC

A Capacitor Mismatch Error Cancelation Technique for High-Speed High-Resolution Pipeline ADC

Systematic design of 10-bit 50MS/s pipelined ADC

A Reconfigurable ADC Circuit with Online-Testing Capability and Enhanced Fault Tolerance

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