A 65nm CMOS comparator with modified latch to achieve 7GHz/1.3mW at 1.2V and 700MHz/47&amp;#x00B5;W at 0.6V

Goll, Bernhard; Zimmermann, Horst

doi:10.1109/isscc.2009.4977441

Cited by 69 publications

(24 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Thus, the effective load capacitance of the latch is reduced in comparison to that of N2 and N3 directly connected to the output nodes. Another reason for the lower input-referred offset is the amplification of CINP-CINN for the initial voltage difference, which causes the latch to switch higher than in other structures (e.g., in [14]), where the input transistors and the latch are parallel (additional parallel load at the output nodes). Disadvantageous is the fact that, due to the many stacked transistors, a sufficient high supply voltage is needed for a proper delay time [11].…”

Section: Introductionmentioning

confidence: 99%

A Comparator With Reduced Delay Time in 65-nm CMOS for Supply Voltages Down to 0.65 V

Goll

Zimmermann

2009

IEEE Trans. Circuits Syst. II

Self Cite

131

View full text Add to dashboard Cite

A comparator in a low-power 65-nm complementary metal-oxide-semiconductor process (only standard transistors with threshold voltage V t ≈ 0.4 V were used) is presented, where the circuit of a conventional latch-type comparator consisting of two cross-coupled inverters is modified for fast operation, even with 0.6 GHz at a low supply voltage of 0.65 V. The advantages of a high-impedance input, rail-to-rail output swing, robustness against the influence of mismatch, and no static power consumption are kept. To achieve a bit error rate of 10 −9 at 1.2-V supply, an amplitude at the input of 16.5 mV at 4 GHz has to be applied. If the supply voltage is lowered, 12.1 mV at 0.6 GHz/0.65 V is necessary. The power consumption of the comparator is 2.88 mW at 5 GHz (1.2 V) and 128 μW at 0.6 GHz (0.65 V). Simulations show an offset standard deviation of about 6.1 mV at 0.65-V supply. With an on-chip measurement circuit, the delay time of the comparator of, e.g., 104 ps for 15-mV input amplitude at 1.2-V supply, is obtained. Index Terms-Comparator, complementary metal-oxidesemiconductor (CMOS) analog circuits, low supply voltage, modified latch, ultradeep submicrometer (UDSM) CMOS.

show abstract

Section: Introductionmentioning

confidence: 99%

A Comparator With Reduced Delay Time in 65-nm CMOS for Supply Voltages Down to 0.65 V

Goll

Zimmermann

2009

IEEE Trans. Circuits Syst. II

Self Cite

131

View full text Add to dashboard Cite

show abstract

“…Table I summarizes the performance of the proposed dynamic comparator. Finally, Table II, compares the performance of the proposed comparator with the designs presented in [6], [9] and [10]. In 90nm CMOS and V DD =0.5V, the proposed comparator provides the maximum sampling of 0.33GHz while consuming 2.3µW power.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…Thus, one of the most effective approaches is to develop new circuit structures which avoid stacking of too many transistors between especially if they do not increase the circuit complexity. In [6], additional circuitry is added to the conventional dynamic comparator to enhance the comparator speed in low supply voltages. Despite effectiveness, the additional circuitry is power hungry and area-inefficient.…”

Section: Introductionmentioning

confidence: 99%

Analysis and design of dynamic comparators in ultra-low supply voltages

Babayan-Mashhadi

Sarvaghad-Moghaddam

2014

2014 22nd Iranian Conference on Electrical Engineering (ICEE)

View full text Add to dashboard Cite

The need for ultra-low power and area-efficient analog-to-digital converters (ADCs) is pushing towards the use of low-voltage (LV) dynamic clocked comparators to maximize power efficiency and speed. In this paper, a delay analysis for a conventional body-driven LV dynamic comparator is presented. Then based on the analysis results, the circuit of a conventional body-driven comparator is modified for fast operation even in small supply voltages. Simulation results in 90nm CMOS technology reveal that comparator delay time is remarkably reduced. The maximum clock frequency of the proposed comparator can be increased to 333 MHz and 50 MHz at supply voltages of 0.5V and 0.35V, while consuming 2.3µW and 184nW, respectively. The standard deviation of the input-referred offset voltage is 5.1mV at 0.5V supply.

show abstract

“…There are many analyses such as noise, offset [5]; random decision errors and kick back noise [6] are present. In this, an analysis of existing clocked regenerative comparators such as conventional dynamic comparator [7][8], double tail comparator [9] and modified double tail comparator [10] is analyzed practically. Based on the results obtained a new dynamic double-tail comparator is proposed which improves the performance over existing comparators.…”

Section: Introductionmentioning

confidence: 99%

Design of a Low Power High Speed Dynamic Double-Tail Comparator

2016

IJAERD

View full text Add to dashboard Cite

show abstract

A 65nm CMOS comparator with modified latch to achieve 7GHz/1.3mW at 1.2V and 700MHz/47µW at 0.6V

Cited by 69 publications

References 4 publications

A Comparator With Reduced Delay Time in 65-nm CMOS for Supply Voltages Down to 0.65 V

A Comparator With Reduced Delay Time in 65-nm CMOS for Supply Voltages Down to 0.65 V

Analysis and design of dynamic comparators in ultra-low supply voltages

Design of a Low Power High Speed Dynamic Double-Tail Comparator

Contact Info

Product

Resources

About