A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors

Chen, Wei-Hao; Li, Kaixiang; Lin, Wei‐Yu; Hsu, Keh‐Ying; Li, Pinyi; Yang, Cheng‐Han; Xue, Cheng-Xin; Yang, En-Yu; Chen, Yen-Kai; Chang, Yun-Sheng; Hsu, Tzu-Hsiang; King, Ya‐Chin; Lin, Chorng-Jung; Liu, Ren-Shuo; Hsieh, Chih-Cheng; Tang, Kea-Tiong; Chang, Meng‐Fan

doi:10.1109/isscc.2018.8310400

Cited by 224 publications

(104 citation statements)

References 4 publications

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“…However, due to the process variation in ReRAM, precisely controlling the resistance of ReRAM with 256 levels is difficult. The reported accuracy of MNIST with MLC ReRAM is 90.8%, less than the reported accuracy using SLC ReRAM [3], [5].…”

Section: B Weight Limitationsmentioning

confidence: 61%

“…In recent years, many ReRAM-based CIM chips have been proposed, with attempts made to balance between accuracy and efficiency while achieving higher precision. A trend to increase the number of I/O and precision of weights has been observed for operations ranging from 1b-input, ternaryweight, 3b-output [3] and 1b-input, 8b-weight, 1b-output [4] to 2b-input, 3b-weight, 4b-output [5] (see Fig. 1).…”

Section: Reram-based Cimmentioning

confidence: 90%

“…To overcome this challenge, numerous high-throughput, low-power devices have been proposed in recent years to reduce the time complexity of matrix-vector multiplications [1], [2]. Moreover, an increasing number of studies have attempted to break the memory wall and reduce the transmission overhead by providing memory with computational ability [3]- [5]. Meanwhile, customized model compression algorithms are essential for the DNNs to be effectively deployed on AI edge devices.…”

Section: Introductionmentioning

confidence: 99%

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A Relaxed Quantization Training Method for Hardware Limitations of Resistive Random Access Memory (ReRAM)-Based Computing-in-Memory

Wei

Jhang

Chen

et al. 2020

IEEE J. Explor. Solid-State Comput. Devices Circuits

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Nonvolatile computing-in-memory (nvCIM) exhibits high potential for neuromorphic computing involving massive parallel computations and for achieving high energy efficiency. nvCIM is especially suitable for deep neural networks, which are required to perform large amounts of matrix-vector multiplications. However, a comprehensive quantization algorithm has yet to be developed, which overcomes the hardware limitations of resistive random access memory (ReRAM)-based nvCIM, such as the number of I/O, word lines (WLs), and ADC outputs. In this article, we propose a quantization training method for compressing deep models. The method comprises three steps: input and weight quantization, ReRAM convolution (ReConv), and ADC quantization. ADC quantization optimizes the error sampling problem by using the Gumbel-softmax trick. Under a 4-bit ADC of nvCIM, the accuracy only decreases by 0.05% and 1.31% for the MNIST and CIFAR-10, respectively, compared with the corresponding accuracies obtained under an ideal ADC. The experimental results indicate that the proposed method is effective for compensating the hardware limitations of nvCIM macros. INDEX TERMS Compression, computing-in-memory (CIM), deep learning, quantization, resistive random access memory (ReRAM).

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Section: B Weight Limitationsmentioning

confidence: 61%

Section: Reram-based Cimmentioning

confidence: 90%

Section: Introductionmentioning

confidence: 99%

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A Relaxed Quantization Training Method for Hardware Limitations of Resistive Random Access Memory (ReRAM)-Based Computing-in-Memory

Wei

Jhang

Chen

et al. 2020

IEEE J. Explor. Solid-State Comput. Devices Circuits

Self Cite

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“…Many ideas of PIMs have been proposed by using SRAM cells [18]- [20] or non-volatile memory (NVM) cells. Especially, NVM based PIMs with such as flash [21], [22], ReRAM [23], [24] or PCM [25], are expected to achieve extremely higher power efficiency thanks to massively parallel execution with multiple weights per cell and no data transfer from outside of the macro to load weigh information. Peripheral circuit design of PIM macros can be quite different from that of normal macros for conventional data storage.…”

Section: Processing-in-memory For E-aimentioning

confidence: 99%

Essential Roles, Challenges and Development of Embedded MCU Micro-Systems to Innovate Edge Computing for the IoT/AI Age

Kimura

Taito

Hidaka

2020

IEICE Trans. Electron.

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Embedded system approaches to edge computing in IoT implementations are proposed and discussed. Rationales of edge computing and essential core capabilities for IoT data supply innovation are identified. Then, innovative roles and development of MCU and embedded flash memory are illustrated by technology and applications, expanding from CPS to big-data and nomadic/autonomous elements of IoT requirements. Conclusively, a technology roadmap construction specific to IoT is proposed.

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“…Since the successful development of the Hewlett-Packard (HP) prototype device [1], memristor has drawn a great deal of research interests [2]. It has been widely used in embedded memory [3,4], neurobiology [5,6], artificial intelligence [7], neural networks [8,9], etc., due to the following advantages: fast speed [10], high density [11], and low power consumption [12,13]. Memristor is a category of nano-devices with nonlinear input-output dynamics.…”

Section: Introductionmentioning

confidence: 99%

Analytic analysis for effects of input initial phase on input-output dynamics of memristor

Wei

Lin

2019

IEICE Electron. Express

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The analytic expressions of input-output dynamic parameters of memristor (i.e., state variable, memristance, and output response) with respect to initial phase of sinusoidal input are obtained by using Homotopy Analysis Method (HAM). Furthermore, a new exponent, called Response Time Delay (difference) between the Maximum Values of input and output-RDMV-IO, is proposed to rapidly analyze the memristor input-output dynamics, under different initial phases. Employing RDMV-IO, we further reveal the intrinsic relationship between initial phase and dynamics. The studies are verified by using Mathematica simulations adopting nonlinear dopant drift memristor model coupled with window function.

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A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors

Cited by 224 publications

References 4 publications

A Relaxed Quantization Training Method for Hardware Limitations of Resistive Random Access Memory (ReRAM)-Based Computing-in-Memory

A Relaxed Quantization Training Method for Hardware Limitations of Resistive Random Access Memory (ReRAM)-Based Computing-in-Memory

Essential Roles, Challenges and Development of Embedded MCU Micro-Systems to Innovate Edge Computing for the IoT/AI Age

Analytic analysis for effects of input initial phase on input-output dynamics of memristor

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