A 650 kV/<i>μ</i>s Common-Mode Resilient CMOS Galvanically Isolated Communication System

Javid, Mahdi; Ptacek, Karel; Burton, R.S.; Kitchen, Jennifer

doi:10.1109/tcsi.2021.3124554

Cited by 8 publications

(6 citation statements)

References 28 publications

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“…The coils are utterly apart from each other, thus separated by a gap purposely for isolated signal transfer. This kind of design is employed at digital/wireless power transfer and galvanically isolated signal transfer 1,21,24 where the gap is filled with a dielectric material. According to this design, the two coils can be excited separately and magnetically coupled with each other for bilateral signal transmission or as a transmitter and a receiver, depending on the circuit design.…”

Section: Laterally-coupled Inductormentioning

confidence: 99%

“…On‐chip coupled inductors are indispensable passive components in radio‐frequency (RF) and mm‐wave integrated circuits (IC) for galvanically isolated power transfer in high‐speed communication networks 1 . Nonetheless, per their inductive intrinsic nature, the performance of on‐chip coupled inductors is frequency variance.…”

Section: Introductionmentioning

confidence: 99%

“…7. Lateral coupling analysis has also been investigated to give better galvanically isolated data transfer as compared with stacked coupling in a high‐speed communication network 1 . To the best of our knowledge a single model which compares both lateral and stacked configurations' performance comprehensively has not yet been reported.…”

Section: Introductionmentioning

confidence: 99%

“…This is to dive into the aspect of lateral coupling reported in Ref. 1, where the structural theoretical analysis of stacked and lateral coupling was compared and the lateral coupling yielded outstanding performance. Though the circuit was implemented with lateral coupling which validates the performance, the hypothetical structures show different inductive areas.…”

Section: Introductionmentioning

confidence: 99%

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Analysis of on‐chip GSG pads coupling effects on laterally‐coupled and double‐stacked inductors in the millimeter‐wave frequency regime

Mawuli

Kang

2023

Int J Numerical Modelling

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On‐chip coupled inductors express huge nonuniform coupling tendencies, especially as frequency increases. This though desirable for wireless/galvanically isolated signal transfer but when mixed with the ground‐signal‐ground (GSG) pad could lead to a misrepresentative of the device's true coupling performance. To determine the coupling between the coupled inductors and that of the GSG pad an integrator analytical model investigating the total coupling effects of the GSG pad on laterally‐coupled and stacked inductors is presented in this study. The model characterizes the lateral and vertical coupling effects using lumped circuit elements with analytical equations. The coupling effects of each component are further decomposed and analyzed as electrical, magnetic, and combined effects. The electrical coupling effect, particularly that of the GSG pad, increases with frequency and impacts significantly on the coupled inductors and the substrate. The mm‐wave frequency characteristics such as skin and proximity effects of the inductors are also modeled by the double RL ladder network. The parameter extraction of the model is based on the measured S‐parameter data. The validation of the proposed model given the measured scattering parameter S21 dB achieves an RMSE of 0.0132 dB at 50 GHz. The inductor typology is most applicable to two‐port networks for impedance matching, cross‐coupled VCOs, and high‐speed communication networks.

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Section: Laterally-coupled Inductormentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Analysis of on‐chip GSG pads coupling effects on laterally‐coupled and double‐stacked inductors in the millimeter‐wave frequency regime

Mawuli

Kang

2023

Int J Numerical Modelling

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“…However, such performance was achieved by means of a stand-alone isolation transformer exploiting 30-µm-thick polyimide layer in a three-chip package. A record of 650-kV/µs CMTI is claimed in [19] by using on-chip lateral coupling at the cost of an isolation rating as low as 5 kV PK . A back-to-back splitring resonators coupler built on a 100-µm laminate film was exploited as on-board isolation component in [20], obtaining an isolation rating of 24 kV with a CMTI of 100 kV/µs and a 10-Gb/s data rate.…”

Section: Introductionmentioning

confidence: 99%

A Three-Channel Package-Scale Galvanic Isolation Interface for Wide Bandgap Gate Drivers

Spina,

Raimondi,

Castorina

et al. 2024

IEEE Trans. VLSI Syst.

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This article presents the design of a three-channel package-scale galvanic isolation interface for SiC and GaN power switching converters. The isolation interface consists of two side-by-side co-packaged chips fabricated in a low-cost 0.32-µm bipolar CMOS-DMOS (BCD) technology and includes three isolation data channels based on RF-coupled integrated microantennas. The isolation interface provides a channel for the gate driver control, a bidirectional channel for diagnostic, and a channel for the isolated power supply control. They use on-off keying (OOK)-modulated RF carriers of 1.5, 0.5, and 1.5 GHz, respectively. The galvanic isolation interface provides a maximum signal rate of 2 and 1.9 MHz for the driver and the power control channels, respectively, whereas the diagnostic channel guarantees half-duplex bidirectional communication up to 15 MHz. Thanks to the package-scale isolation approach, both reinforced galvanic isolation and first-rate common-mode transient immunity (CMTI) are achieved. High immunity to adjacent channel crosstalk is guaranteed by using channel frequency/physical separation. To best of the authors' knowledge, this is the first implementation of a package-scale galvanic isolation interface with three independent communication channels, including a bidirectional channel, in silicon technology.

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16-Cell stackable battery monitoring and management integrated circuit for electric vehicles

Zhu

Qian

et al. 2023

Microelectronics Journal

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A 650 kV/μs Common-Mode Resilient CMOS Galvanically Isolated Communication System

Cited by 8 publications

References 28 publications

Analysis of on‐chip GSG pads coupling effects on laterally‐coupled and double‐stacked inductors in the millimeter‐wave frequency regime

Analysis of on‐chip GSG pads coupling effects on laterally‐coupled and double‐stacked inductors in the millimeter‐wave frequency regime

A Three-Channel Package-Scale Galvanic Isolation Interface for Wide Bandgap Gate Drivers

16-Cell stackable battery monitoring and management integrated circuit for electric vehicles

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