A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors

Torrens, Gabriel; Alorda, B.; Carmona, Cristian; Malagon-Perianez, Daniel; Segura, J.; Bota, S.

doi:10.1109/tetc.2017.2721932

Cited by 29 publications

(23 citation statements)

References 32 publications

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“…One of the suggested solutions to the power dissipation problem is to scale back the power supply, but the reliability of the SRAM cell poses another challenge in this. Besides this, issues like data stability, delay and high sensitivity to process variation [7][8][9][10][11][12] also contributes to overall performance of SRAM. and two PMOS (PM 3 and PM 4 ) transistors.…”

Section: Related Workmentioning

confidence: 99%

“…At the scaled cell supply voltage, the 6T SRAM cell encounters several issues like stability, delay, high sensitivity to process variation etc. [11]. The SRAM cell stability is mainly affected by the strength of transistors which form internal latch and access transistors.…”

Section: Related Workmentioning

confidence: 99%

“…As a result, the cell is less stable at lower supply voltages than it is at higher supply voltages. Additionally, when developed at 1 V supply voltage using the same technology node, the WSNM of the suggested design is improved by 48%, 11%, 19%, and 32.4% over basic 6T SRAM cell [11], NBL[16], VDD collapse [17], and 9T UV SRAM [19], respectively. This increase was made possible by a negative bit-increased line's ability to boost the access transistor's VGS.…”

Section: Write Abilitymentioning

confidence: 99%

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WITHDRAWN: Low Leakage Variation SRAM Cell with Improved Stability for IOT Applications

Rawat

Kumar

2022

Preprint

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The typical memory for very large scale integrated (VLSI) circuits has traditionally been static random access memory (SRAM). This is so because SRAM is a speedier technology than the ones that were previously mentioned. SRAM, however, has a high power consumption rate. Due to its importance in the memory architecture, it is crucial to lower the power consumption of SRAM cells. This literature review's major goal is to provide innovative and effective strategies for creating low power SRAM cells. This study provides several circuit topologies and methodologies to compute stability, leakage current, delay, and power, as well as novel techniques for designing SRAM cells based on eight transistors (8T). The static random access memory (SRAM) is frequently chosen over dynamic random access memory (DRAM) due to faster speed and lower power consumption. It is named static since no modification or action, i.e. refreshing, is required to maintain the data intact. The leakage current in SRAM, however, frequently rises and impairs its performance when technology nodes are scaled down. Voltage scaling, which also impacts the stability and latency of SRAM, is chosen as a solution to this problem. In this study, a separate (isolated) read port is employed to increase read stability while a negative bit-line (NBL) write aid circuit is used to improve write capability. In terms of write static noise margin (WSNM), write latency, read static noise margin (RSNM), and other metrics, the suggested design has been compared to state-of-the-art work. The following is how the paper is divided into sections: 1. Introduction. Section 2 describes related work. The suggested work is in section 3. Results and discussion are included in section 4 and section 5 Conclusions.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Write Abilitymentioning

confidence: 99%

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WITHDRAWN: Low Leakage Variation SRAM Cell with Improved Stability for IOT Applications

Rawat

Kumar

2022

Preprint

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“…SRAM designs can be categorized based on interconnections with the inverter as i) cross-coupled standard inverter, ii) cross-coupled Schmitt-trigger (ST) inverter, and iii) cross-coupled ST inverter with a standard inverter. First, various inverters that fall under the crosscoupled standard inverter category are the conventional 6T [17], 8T [18], Pasandi's 9T [19], Chang's 9T [20], Joon's 10T [21], and 7T [22]. In 10T SRAM, a single BL is used for both read/write to reduce the power consumption [23], and in 11T, power gating transistors and a transmission gate are implemented to reduce the power leakage [24].…”

Section: Introductionmentioning

confidence: 99%

Design of Low Power Transmission Gate Based 9T SRAM Cell

Rooban¹,

Leela²,

Rahman³

et al. 2022

Computers, Materials &Amp; Continua

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Considerable research has considered the design of low-power and high-speed devices. Designing integrated circuits with low-power consumption is an important issue due to the rapid growth of high-speed devices. Embedded static random-access memory (SRAM) units are necessary components in fast mobile computing. Traditional SRAM cells are more energyconsuming and with lower performances. The major constraints in SRAM cells are their reliability and low power. The objectives of the proposed method are to provide a high read stability, low energy consumption, and better writing abilities. A transmission gate-based multi-threshold single-ended Schmitt trigger (ST) 9T SRAM cell in a bit-interleaving structure without a write-back scheme is proposed. Herein, an ST inverter with a single bit-line design is used to attain the high read stability. A negative assist technique is applied to alter the trip voltage of the single-ended ST inverter. The multithreshold complementary metal oxide semiconductor (MTCMOS) technique is adopted to reduce the leakage power in the proposed single-ended TG-ST 9T SRAM cell. The proposed system uses a combination of standard and ST inverters, which results in a large read stability. Compared with the previous ST 9T, ST 11T, 11T, 10T, and 7T SRAM cells, the proposed cell is implemented in Cadence Virtuoso ADE with 45-nm CMOS technology and consumes 35.80%, 42.09%, 31.60%, 12.54%, and 31.60% less energy for read operations and 73.59%, 93.95%, 92.76%, 89.23%, and 85.78% less energy for write operations, respectively.

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“…During learning measure, little lines communicate information from SRAM cells to a sound enhancer. In fact, the base length of the semiconductors is 180 nm CMOS[17].…”

mentioning

confidence: 99%

Restoration circuits for low power reduce swing of 6T and 8T SRAM cell with improved read and write margins

Rawat

Kumar

2021

IJRES

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<span>This article clarifies about the variables that influence the static noise margin (SNM) of a static random-access memory. Track down the improved stability of proposed 8T SRAM cell which is superior to conventional 6T SRAM cell utilizing Swing Restored circuit with voltages Q and QB bar are peruse and Compose activity. This SRAM cell strategy on the circuit or engineering level is needed to improve read static noise margin (RSNM), write static noise margin (WSNM) and hold static noise margin (HSNM). This article relative investigation of conventional 6T, standard 8T and proposed 8T SRAM cells with improved stability and static noise margin is finished for 180 nm CMOS innovation. This paper is coordinated as follows: Introduction in area 1, The 6T SRAM cell are portrayed in segment 2. In area 3, proposed 8T SRAM cell is portrayed. In area 4, standard 8T SRAM cell. Segment 5 incorporates the simulation and results which give examination of different boundaries of 6T and 8T SRAM cells and segment 6 conclusions.</span>

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A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors

Cited by 29 publications

References 32 publications

WITHDRAWN: Low Leakage Variation SRAM Cell with Improved Stability for IOT Applications

WITHDRAWN: Low Leakage Variation SRAM Cell with Improved Stability for IOT Applications

Design of Low Power Transmission Gate Based 9T SRAM Cell

Restoration circuits for low power reduce swing of 6T and 8T SRAM cell with improved read and write margins

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