A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load

Ojima, Naoki; Nakura, Toru; Iizuka, Tetsuya; Asada, Kunihiro

doi:10.1007/978-3-030-23425-6_1

Cited by 1 publication

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“…For a typical analog component, its layout has to be manually re-designed every time the specification changes even slightly. Recently, synthesizable or automated designs of analog building blocks have been widely studied in order to relax the burden of manual analog designs [14,15,16,17,18,19,20,21,22,23]. In addition, in some applications such as IoT (Internet of Things) [24], these devices are typically highly duty-cycled, hence sleep and startup power consumption often dominates the total power budget.…”

Section: Introductionmentioning

confidence: 99%

A compact quick-start sub-mW pulse-width-controlled PLL with automated layout synthesis using a place-and-route tool

Wang

Iizuka

et al. 2019

IEICE Electron. Express

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This paper demonstrates the design flow of a quick-start pulsewidth-controlled PLL with automated layout synthesis using a place-androute tool. The quick-start PWPLL converts the internal state into an analog-digital mixed signal called soft-thermometer-code (STC) and stores them into memory before PWPLL is turned off in order to enhance the start-up in the next turn-on. Our chip fabricated with TSMC 65 nm shows 220 ns settling time (13 reference clock cycles), 858 µW power consumption under 1 V nominal supply voltage with 59 µm × 58 µm silicon area. The measurement results demonstrate that the design-automated PLL realizes the FoM of −221.7 dB, which is roughly the same value as that of the manually-designed one with the same target specification.

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