A 64Mb SRAM in 22nm SOI technology featuring fine-granularity power gating and low-energy power-supply-partition techniques for 37% leakage reduction

Pilo, H.; Adams, Comfort A.; Arsovski, Igor; Houle, R.; Lamphier, S.; Lee, M. M.; Pavlik, Frank; Sambatur, S. N.; Seferagic, Adnan; Wu, Ryan; Younus, M. I.

doi:10.1109/isscc.2013.6487753

Cited by 23 publications

(14 citation statements)

References 5 publications

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“…2% as reported in [14], which means SRAM cells are idle for most of the time. Accordingly, the leakage power becomes the dominant component of the power consumption of SRAMs [3]. Hence, without loss of generality, our objective is to minimize the expectation of the leakage energy consumption (in each clock cycle) of an SRAM cell such that read stability and writeability requirements under process variations are met.…”

Section: B Optimization Frameworkmentioning

confidence: 99%

“…Moreover, SRAM cells have relatively low activity factors, and hence long idle periods. As a result, the leakage power of SRAMs not only dominates the power consumption of the memory circuit but also becomes a major component of the overall chip power consumption [3]. An effective solution to reduce the leakage power without significantly sacrificing performance is to scale down the supply voltage to an operating point (typically in the near-threshold region) where energy consumption is minimized [4].…”

Section: Introductionmentioning

confidence: 99%

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A cross-layer framework for designing and optimizing deeply-scaled FinFET-based SRAM cells under process variations

Shafaei

Chen

Wang

et al. 2015

The 20th Asia and South Pacific Design Automation Conference

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A cross-layer framework (spanning device and circuit levels) is presented for designing robust and energy-efficient SRAM cells, made of deeply-scaled FinFET devices. In particular, 7nm FinFET devices are designed and simulated by using Synopsys TCAD tool suite, Sentaurus. Next, 6T and 8T SRAM cells, which are composed of these devices, are designed and optimized. To enhance the cell stability and reduce leakage energy consumption, the dual (i.e., front and back) gate control feature of FinFETs is exploited. This is, however, done without requiring any external signal to drive the back gates of the FinFET devices. Subsequently, the effect of process variations on the aforesaid SRAMs is investigated and steps are presented to protect the cells against these variations. More precisely, the SRAM cells are first designed to minimize the expected energy consumption (per clock cycle) subject to the non-destructive read and successful write requirements under worst-case process corner conditions. These SRAM cells, which are overly pessimistic, are then refined by selectively adjusting some transistor sizes, which in turn reduces the expected energy consumption while ensuring that the parametric yield of the cells remains above some prespecified threshold. To do this efficiently, an analytical method for estimating the yield of SRAM cells under process variations is also presented and integrated in the refinement procedure. A dual-gate controlled 6T SRAM cell operating at 324mV (in the near-threshold supply regime) is finally presented as a high-yield and energy-efficient memory cell in the 7nm FinFET technology.

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Section: B Optimization Frameworkmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A cross-layer framework for designing and optimizing deeply-scaled FinFET-based SRAM cells under process variations

Shafaei

Chen

Wang

et al. 2015

The 20th Asia and South Pacific Design Automation Conference

View full text Add to dashboard Cite

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“…The same can't be done for the memory used in the system: the entire memory module is manufactured from the same type of cells, which use either high performance or low standby power type transistors. HP SRAM reaches higher clock speeds but a substantial amount of current leakage is present [3]. The slower LSTP SRAM is used to minimize leakage, but the memory cells have higher on-currents, consuming more dynamic power as a trade-off.…”

Section: Power Consumptionmentioning

confidence: 99%

“…If high performance (HP) SRAM is used on the chip, a substantial amount of current leakage is present [3]. Slower low standby power (LSTP) SRAM can be used to avoid large leakage, but LSTP memory cells have higher on-currents, consuming more dynamic power as a tradeoff.…”

Section: Introductionmentioning

confidence: 99%

Variable length instruction compression on Transport Triggered Architectures

Helkala

Viitanen

Kultala

et al. 2014

2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)

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The Static Random-Access Memory (SRAM) modules used for embedded microprocessor devices consume a large portion of the whole system's power. The memory module consumes static power on keeping awake and dynamic power on memory accesses. The power dissipation of the instruction memory can be limited by using code compression methods, which reduce the memory size. The compression may require the use of variable length instruction formats in the processor. The powerefficient design of variable length instruction fetch and decode units is challenging for static multiple-issue processors, because such architectures have simple hardware to begin with, as they aim for very low power consumption on embedded platforms. The power saved by using these compression approaches, which necessitate more complex logic, is easily lost on inefficient processor design.This thesis proposes an implementation for instruction template-based compression, its decompression and two instruction fetch design alternatives for variable length instruction encoding on Transport Triggered Architecture (TTA), a static multiple-issue exposed data path architecture. Both of the new fetch and decode units are integrated into the TTA-based Co-design Environment (TCE), which is a toolset for rapid designing and prototyping of processors based on TTA.The hardware description of the fetch units is verified on a register transfer level and benchmarked using the CHStone test suite. Furthermore, the fetch units are synthesized on a 40 nm standard cell Application Specific Integrated Circuit (ASIC) technology library for area, performance and power consumption measurements. The power cost of the variable length instruction support is compared to the power savings from memory reduction, which is evaluated using HP Labs' CACTI tool.The compression approach reaches an average program size reduction of 44% at best with a set of test programs, and the total power consumption of the system is reduced. The thesis shows that the proposed variable length fetch designs are sufficiently low-power oriented for TTA processors to benefit from the code compression.

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“…This method is widely used to decrease leakage of circuits in standby mode. Several optimised and efficient versions of this method have been introduced in numerous papers (Pakbaznia & Pedram, 2012;Pilo et al, 2013;Wang, Ohta, Ishii, Usami, & Amano, 2012). This technique is also implemented in RAMs with CMOS and other transistors (Ohsawa et al, 2012).…”

Section: Introductionmentioning

confidence: 99%

A new low-power 10T SRAM cell with improved read SNM

Pasandi

Jafari

Imani

2015

International Journal of Electronics

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This paper describes the characteristics of a new 10T structure for SRAM cell that works quite well in the sub-threshold region. This new architecture has good characteristics in write and read delay and energy compared with other new structures. This new 10T topology improves read static noise margin (SNM) and write operation speed with respect to other topologies in the same or even lower power consumption. The new topology has at least 13% lower power consumption compared with the best of recent architectures. Its write characteristics also are similar to those of 6T-SRAM, which has improved write delay and energy. The new 10T SRAM cell also consumes lower power compared with other cells. The stacking is used to suppress the standby leakage through the read path. The simulations were performed using HSPICE 2011 in a 16 nm bulk CMOS Berkeley predictive technology model (BPTM).

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A 64Mb SRAM in 22nm SOI technology featuring fine-granularity power gating and low-energy power-supply-partition techniques for 37% leakage reduction

Cited by 23 publications

References 5 publications

A cross-layer framework for designing and optimizing deeply-scaled FinFET-based SRAM cells under process variations

A cross-layer framework for designing and optimizing deeply-scaled FinFET-based SRAM cells under process variations

Variable length instruction compression on Transport Triggered Architectures

A new low-power 10T SRAM cell with improved read SNM

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