A new low-power 10T SRAM cell with improved read SNM

Abstract

This paper describes the characteristics of a new 10T structure for SRAM cell that works quite well in the sub-threshold region. This new architecture has good characteristics in write and read delay and energy compared with other new structures. This new 10T topology improves read static noise margin (SNM) and write operation speed with respect to other topologies in the same or even lower power consumption. The new topology has at least 13% lower power consumption compared with the best of recent architectures. Its write characteristics also are similar to those of 6T-SRAM, which has improved write delay and energy. The new 10T SRAM cell also consumes lower power compared with other cells. The stacking is used to suppress the standby leakage through the read path. The simulations were performed using HSPICE 2011 in a 16 nm bulk CMOS Berkeley predictive technology model (BPTM).

Estimation of Write Noise Margin for 6t SRAM Cell in CMOS 45nm technology.

“…The write propagation delay is calculated by measuring the individual output delay at low-high and high-low states at half of the supply. The static noise margin (SNM) probably determines the noise in the SRAM cell, where as the WNM is calculated by considering the difference between W/L ratios of M4 (access transistor) & M6 (load transistor) transistor [5][6] using DC analysis, the measured value is 2.06v (at successive points of NM-low and NM-high differences) as in Fig. 4.…”

A new 7T SRAM cell in sub‐threshold region with a high performance and small area with bit interleaving capability

“…The 6T cell has a high power consumption [1, 2]. According to the literature, the most effective method for reducing power consumption is cell design in sub‐threshold region on lower VDDs [3]. Whereas reducing the cell's power supply makes many problems in the cell and impairs its performance [4].…”