A 64Kb full CMOS RAM with divided word line structure

Yoshimoto, Masahiko; Anami, Keiko; Shinohara, Hirofumi; Yoshihara, Tsutomu; Takagi, Hiromitsu; Nagao, Shijo; Kayano, S.; Nakano, T.

doi:10.1109/isscc.1983.1156503

Cited by 40 publications

(9 citation statements)

References 3 publications

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“…The memory architecture and decoder organization are shown in Figure 1. A dual bank row-decoder, as well as the Divided Word Line scheme [3] have been used to reduce power consumption, through a partial activation of multi-divided wordlines. The memory is divided into 2 banks of 16 x 4Kbit pages.…”

Section: Generator Featuresmentioning

confidence: 99%

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A low voltage embedded single port SRAM generator in a 0.18 μm standard CMOS process

Frey¹,

Genevaux

Issartel

et al.

Records of the IEEE International Workshop on Memory Technology, Design and Testing

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memCell Voltage range A low voltage embedded single port SRAM memory generator implemented in a 6 metals, 0. I8um standard CMOS process is described. The typical (8kx16) cut is achieving 300Mhz maximum frequency, with a 3.3ns access time at 1.3V and 25°C and a typical power of 6OpVMhz at 1.3V Special care has been taken to reduce the standby current as well. The hierarchical wordline architecture, and a diflerential output bus allow low power characteristics. At the same time high speed is reached, especially thanks to a novel dynamic wordline decoder: The generator ranges from I Kbit to 2Mbit and features an optional programmable redundancy. 6 transistors memory cell with local interconnect. Area = 4.9@& 0.9v to 2.0v Wordsize: 8 to 728 number of Words: 728 to 728K Biggest cut is 64K x 32 (2Mb).

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Section: Generator Featuresmentioning

confidence: 99%

“…The Divided Word Line [3] architecture reduces the number of active memory cells, through partial activation of local wordlines. Only 32 cells on a line of 512 are activated.…”

Section: Memory Corementioning

confidence: 99%

A low voltage embedded single port SRAM generator in a 0.18 μm standard CMOS process

Frey¹,

Genevaux

Issartel

et al.

Records of the IEEE International Workshop on Memory Technology, Design and Testing

View full text Add to dashboard Cite

show abstract

“…Low power SRAM design techniques are mainly based on reducing the capacitance and the voltage swing level. Bit lines, word lines and data lines are the largest capacitive parts in the memory [3][4][5][6]. Divided Word Line (DWL) technique is used to reduce the word lines capacitance [3].…”

Section: Introductionmentioning

confidence: 99%

“…Bit lines, word lines and data lines are the largest capacitive parts in the memory [3][4][5][6]. Divided Word Line (DWL) technique is used to reduce the word lines capacitance [3]. Half swing technique shows about 45% bit lines power reduction can be achieved by reducing the bit line swing to 0.5 VDD [4].…”

Section: Introductionmentioning

confidence: 99%

Novel 7T sram cell for low power cache design

Aly

Faisal

Bayoumi

2005 Joint 30th International Conference on Infrared and Millimeter Waves and 13th International Conference on Terahertz Electr

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Low-power on-chip cache is a crucial part in many applications. Conventional write operation depends on discharging/charging large bit lines capacitance which causes high power consumption. We propose a novel 7T SRAM cell that only depends on one of the bit lines during a write operation and reduce the write power consumption. HSPICE simulation shows that at least 49% write power saving, higher stability, and no performance degradation with additional 12.25% silicon area.

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“…Techniques have been proposed to reduce the write power consumptions that mainly try to reduce the switched capacitance and/or the voltage swing level on the bit lines [2][3][4][5][6]. Half swing technique shows about 45% write power reduction by reducing the bit line swing to 0.5 VDD [2].…”

Section: Introductionmentioning

confidence: 99%

Precharged sram cell for ultra low-power on-chip cache

Aly

Bayoumi

2005 Joint 30th International Conference on Infrared and Millimeter Waves and 13th International Conference on Terahertz Electr

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ABSTARACTThis paper proposes an ultra low-power technique to reduce dynamic and leakage power in SRAM. At write mode, the technique reduces the voltage swing required on the bit lines and depends on the cell itself to amplify the small swing to full swing. HSPICE simulation shows 94.2% write power saving in 0. 18pm technology. On the sleep mode, the proposed cell reduces the leakage current by 60% for 70nm technology.

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A 64Kb full CMOS RAM with divided word line structure

Cited by 40 publications

References 3 publications

A low voltage embedded single port SRAM generator in a 0.18 μm standard CMOS process

A low voltage embedded single port SRAM generator in a 0.18 μm standard CMOS process

Novel 7T sram cell for low power cache design

Precharged sram cell for ultra low-power on-chip cache

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