A 64-tap CMOS echo canceller/decision feedback equalizer for 2B1Q HDSL transceivers

Samueli, H.; Daneshrad, Babak; Joshi, R.B.; Wong, B.C.; Nicholas, H.T.

doi:10.1109/49.93094

Cited by 33 publications

(8 citation statements)

References 4 publications

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“…For coefficient output, each coefficient is connected to an output bus by a tri-state buffer. The buffer is controlled by a one bit wide and 96 bit long shift register whose length is equal to the total number of coefficients [4]. Thus, there will only be one bit high in the one bit shift register and therefore only one coefficient can pass to the output bus through its tri-state buffer.…”

Section: Programmable Low Power Filtermentioning

confidence: 99%

Low power signal processing architectures for network microsensors

Dong

Yung

Kaiser

1997

Proceedings of the 1997 International Symposium on Low Power Electronics and Design - ISLPED '97

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Low power signal processing systems are required for distributed network microsensor technology.Network microsensors now provide a new monitoring and control capability for civil and military applications in transportation, manufacturing, biomedical technology, environmental management, and safety and security systems. Signal processing methods for event detection have been developed with low power, parallel architectures that optimize performance for unique sensor system requirements. Implementation of parallel datapatbs with shared arithmetic elements enables high throughput at low clock rate. This method has been used to implement a microsensor spectrum analyzer for a 200 sample/s measurement system. This 0.8p CMOS device operates with a 1M drain current at a 3V supply bias.

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Section: Programmable Low Power Filtermentioning

confidence: 99%

Low power signal processing architectures for network microsensors

Dong

Yung

Kaiser

1997

Proceedings of the 1997 International Symposium on Low Power Electronics and Design - ISLPED '97

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“…High rate data transmission over copper wire has received considerable attention in the recent past [4] [8]- [13] [23]- [25] due to the desire of telephone operating companies to transmit high rate digital data over their existing infrastructure of copper loops [1] [4]. These efforts have given rise to standards and products for Basic-Rate digital subscriber loop (DSL) services [2][3], high-speed DSL (HDSL) services [6] [7], and more recently, asymmetric DSL (ADSL) services.…”

Section: Introductionmentioning

confidence: 99%

A 1.6 Mbps digital-QAM system for DSL transmission

Daneshrad¹,

Samueli²

1995

IEEE J. Select. Areas Commun.

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An all digital QAM system is studied here for high-speed data transmission on digital subscriber loops. All elements of the system have been fully investigated and their effects on the overall system performance documented. In particular the following issues have been explicitly addressed: utility of an adaptive error-prediction (noise-prediction) filter; equalizer size and convergence; blind equalization; choice of constellation size and center frequency; combined timing/ carrier recovery, and finally the oversampling requirements of an NCO for potential use in the timing and carrier recovery loop. The paper relies on simulation results to investigate and quantify the overall interactions of the various blocks. Throughout the paper emphasis has been placed on reducing the complexity of the system for implementation on an integrated circuit (IC). It is expected that the information provided here will serve as a good starting point for an IC designer to start the implementation of a transceiver ASIC. .

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“…In a broad sense, the term equalization can be used to describe any signal processing operation that minimizes the ISI. Two of the most intensively developing areas of digital transmission, namely digital subscriber lines (DSL) and cellular communication (GSM) are strongly dependent on the realization of reliable channel equalizers [3,4,5]. www.ijacsa.thesai.org…”

Section: Introductionmentioning

confidence: 99%

Improving the Rate of Convergence of Blind Adaptive Equalization for Fast Varying Digital Communication Systems

E.Tersoo¹,

Kolawole²

2012

IJACSA

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Abstract-The recent digital transmission systems impose the application of channel equalizers with bandwidth efficiency, which mitigates the bottleneck of intersymbol interference for high-speed data transmission-over communication channels. This leads to the exploration of blind equalization techniques that do not require the use of a training sequence. Blind equalization techniques however suffer from computational complexity and slow convergence rate. The Constant Modulus Algorithm (CMA) is a better technique for blind channel equalization. This paper examined three different error functions for fast convergence and proposed an adaptive blind equalization algorithm with variable step size based on CMA criterion. A comparison of the existing and proposed algorithms' speed of convergence shows that the proposed algorithm outperforms the other algorithms. The proposed algorithm can suitably be employed in blind equalization for rapidly changing channels as well as for high data rate applications.

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A 64-tap CMOS echo canceller/decision feedback equalizer for 2B1Q HDSL transceivers

Cited by 33 publications

References 4 publications

Low power signal processing architectures for network microsensors

Low power signal processing architectures for network microsensors

A 1.6 Mbps digital-QAM system for DSL transmission

Improving the Rate of Convergence of Blind Adaptive Equalization for Fast Varying Digital Communication Systems

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