A 64-core platform for biomedical signal processing

Bisasky, Jordan; Homayoun, Houman; Yazdani, Farhang

doi:10.1109/isqed.2013.6523637

Cited by 11 publications

(7 citation statements)

References 19 publications

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“…Among the many commonalities shared between personal biomedical applications, the need to process parallel streams of data in real-time is a dominating feature. The analysis of these multiple streams requires a mix of data-level and task-level parallel computation [3,6,2,1]. In addition, these applications often require a large number of digital signal processing (DSP) and machine learning (ML) techniques.…”

Section: Biomedical Applicationsmentioning

confidence: 99%

Low-Power Manycore Accelerator for Personalized Biomedical Applications

Page

Attaran

Shea

et al. 2016

Proceedings of the 26th Edition on Great Lakes Symposium on VLSI

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Wearable personal health monitoring systems can offer a cost effective solution for human healthcare. These systems must provide both highly accurate, secured and quick processing and delivery of vast amount of data. In addition, wearable biomedical devices are used in inpatient, outpatient, and at home e-Patient care that must constantly monitor the patient's biomedical and physiological signals 24/7. These biomedical applications require sampling and processing multiple streams of physiological signals with strict power and area footprint. The processing typically consists of feature extraction, data fusion, and classification stages that require a large number of digital signal processing and machine learning kernels. In response to these requirements, in this paper, a lowpower, domain-specific manycore accelerator named Power Efficient Nano Clusters (PENC) is proposed to map and execute the kernels of these applications. Experimental results show that the manycore is able to reduce energy consumption by up to 80% and 14% for DSP and machine learning kernels, respectively, when optimally parallelized. The performance of the proposed PENC manycore when acting as a coprocessor to an Intel Atom processor is compared with existing commercial off-the-shelf embedded processing platforms including Intel Atom, Xilinx Artix-7 FPGA, and NVIDIA TK1 ARM-A15 with GPU SoC. The results show that the PENC manycore architecture reduces the energy by as much as 10X while outperforming all off-the-shelf embedded processing platforms across all studied machine learning classifiers. CCS Concepts •Computer systems organization → Architectures; •Computing methodologies → Parallel computing methodologies; Machine learning algorithms; •Applied computing → Bioinformatics;

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Section: Biomedical Applicationsmentioning

confidence: 99%

Low-Power Manycore Accelerator for Personalized Biomedical Applications

Page

Attaran

Shea

et al. 2016

Proceedings of the 26th Edition on Great Lakes Symposium on VLSI

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“…It consists of 64 low-power small cores [12], [13]. Each core operates on a 16-bit data-path with a minimal instruction and data memory suitable for task level parallelism.…”

Section: B Domain Specific Many-corementioning

confidence: 99%

Accelerating compressive sensing reconstruction OMP algorithm with CPU, GPU, FPGA and domain specific many-core

Kulkarni

2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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Compressive Sensing (CS) signal reconstruction can be implemented using convex relaxation, non-convex, or local optimization algorithms. Though the reconstruction using convex optimization, such as the Iterative Hard Thresholding algorithm, is more accurate than matching pursuit algorithms, most researchers focus on matching pursuit algorithms because they are less computationally complex. Orthogonal Matching Pursuit (OMP) is a greedy algorithm, which solves the problem by choosing the most significant variable to reduce the least square error. In this paper, we propose an efficient parallel architecture for OMP CS reconstruction. For architecture implementation, we perform measurement and sparsity analysis to reduce the complexity. The proposed architecture is platform independent and is implemented on 7 different platforms including general purpose CPUs, GPUs, a Virtex-7 FPGA and a domain specific many-core. The implementation results indicate that reconstruction time on FPGA is improved by 3× compared to previous FPGA implementation, whereas GPU implementation is 4× faster than the previously proposed GPU-based OMP architecture. The CPU implementation is 6× faster, compared with previous CPUbased implementation. The domain specific many-core acheives 24 times faster reconstruction time when compared to both GPU and CPU implementations.

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“…Functional unit conflicts occur when the processor pipeline has ready instructions, but not available functional units of particular type (multiplier, for instance) to execute. Note that in spite of high functional unit conflicts, it is not design efficient to increase the number of functional units in processor pipeline, as the complexity of additional functional unit will be significant [6,13,15]. As studied in several works, increasing the number of functional units not only increases the power consumption of the processor but also significantly affects the complexity of several back-end pipeline stages including instruction queue, write-back buffers, bypass stage, register file design and could severely affect the processor performance, as the number of write-back ports increase significantly [6].…”

Section: Motivationmentioning

confidence: 99%

Reconfigurable STT-NV LUT-based functional units to improve performance in general-purpose processors

Ashammagari

Mahmoodi

Homayoun

2014

Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI

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Unavailability of functional units is a major performance bottleneck in general-purpose processors (GPP). In a GPP with limited number of functional units while a functional unit may be heavily utilized at times, creating a performance bottleneck, the other functional units might be under-utilized. We propose a novel idea for adapting functional units in GPP architecture in order to overcome this challenge. For this purpose, a selected set of complex functional units that might be under-utilized such as multiplier and divider, are realized using a programmable look up table-based fabric. This allows for run-time adaptation of functional units to improving performance. The programmable look up tables are realized using magnetic tunnel junction (MTJ) based memories that dissipate near zero leakage and are CMOS compatible. We have applied this idea to a dual issue architecture. The results show that compared to a design with all CMOS functional units a performance improvement of 18%, on average is achieved for standard benchmarks. This comes with 4.1% power increase in integer benchmarks and 2.3% power decrease in floating point benchmarks, compared to a CMOS design.

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A 64-core platform for biomedical signal processing

Cited by 11 publications

References 19 publications

Low-Power Manycore Accelerator for Personalized Biomedical Applications

Low-Power Manycore Accelerator for Personalized Biomedical Applications

Accelerating compressive sensing reconstruction OMP algorithm with CPU, GPU, FPGA and domain specific many-core

Reconfigurable STT-NV LUT-based functional units to improve performance in general-purpose processors

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