A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference

Gallo, Manuel Le; Khaddam-Aljameh, Riduan; Stanisavljević, Miloš; Vasilopoulos, Athanasios; Kersting, Benedikt; Dazzi, Martino; Karunaratne, Geethan; Braendli, Matthias; Singh, Abhairaj; Mueller, Silvia Melitta; Julian, Buechel,; Timoneda, Xavier; Joshi, Vinay; Egger, Urs; Garofalo, Angelo; Πετρόπουλος, Αναστάσιος; Antonakopoulos, Theodore; Brew, Kevin; Choi, Samuel; Ok, I.; Philip, Timothy M.; Chan, Victor; Silvestre, Claire; Ahsan, Ishtiaq; Saulnier, Nicole; Narayanan, Vijaykrishnan; Francese, Pier Andrea; Eleftheriou, Evangelos; Sebastian, Abu

doi:10.48550/arxiv.2212.02872

Cited by 1 publication

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“…Even with significant weight reuse, each MVM operation comes with significant memory access overhead . A promising compute paradigm that aims to address this is analog CIM. − The essential idea is to fabricate a weight stationary array of synaptic unit cells based on ultradense memory devices (see Figure b). Each unit cell holds one synaptic weight that can remain stationary for many inferences.…”

Section: Computing-in-memory System For Ai Acceleratorsmentioning

confidence: 99%

“…Wan et al developed a multicore CIM chip to perform diversity tasks with high accuracy . Recently, IBM reports a multicore CIM chip with complete on-chip routing solution, making important progress on the completeness of the CIM system.…”

Section: Computing-in-memory System For Ai Acceleratorsmentioning

confidence: 99%

“…Figure shows a compute core that is based on PCM embedded in an advanced 14 nm CMOS technology node. , Compact current controlled-oscillator-based ADCs allow the MVM operation to be executed at constant time complexity without requiring any time-multiplexing, since the pitches of the ADCs and the unit cells match. Despite the integration of the PCM element at a relatively high position in the metal stack, a throughput density of 1.59 TOPS/mm 2 is achieved.…”

Section: Computing-in-memory System For Ai Acceleratorsmentioning

confidence: 99%

“…It comprises 256 × 256 array of synaptic units . (b) Each synaptic unit cell comprises 4 PCM devices onto which the synaptic weights are mapped in terms of the analog conductance value of the devices arising from the underlying phase configuration of the devices . (c) Backend of the line integration of PCM devices …”

Section: Computing-in-memory System For Ai Acceleratorsmentioning

confidence: 99%

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Recent Advances and Future Prospects for Memristive Materials, Devices, and Systems

et al. 2023

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Memristive technology has been rapidly emerging as a potential alternative to traditional CMOS technology, which is facing fundamental limitations in its development. Since oxide-based resistive switches were demonstrated as memristors in 2008, memristive devices have garnered significant attention due to their biomimetic memory properties, which promise to significantly improve power consumption in computing applications. Here, we provide a comprehensive overview of recent advances in memristive technology, including memristive devices, theory, algorithms, architectures, and systems. In addition, we discuss research directions for various applications of memristive technology including hardware accelerators for artificial intelligence, in-sensor computing, and probabilistic computing. Finally, we provide a forward-looking perspective on the future of memristive technology, outlining the challenges and opportunities for further research and innovation in this field. By providing an up-to-date overview of the state-of-the-art in memristive technology, this review aims to inform and inspire further research in this field.

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