A 64-Bit Arm CPU at Cryogenic temperatures: Design Technology Co-Optimization for Power and Performance

Saligram, Rakshith; Prasad, Divya; Pietromonaco, David; Raychowdhury, Arijit; Cline, Brian

doi:10.1109/cicc51472.2021.9431559

Cited by 12 publications

(6 citation statements)

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“…12(a). One of the key take-away from [2] was that the internal power of the system increases by 77% going from 300K to 100K. This can be clearly explained from the BSIM4 models where we notice that ISC increases going from 300K to 6K due to higher ION with ~20% increase in the peak value for input slew of 20ps for a 1x inverter driving a nominal 1fF load.…”

Section: B Inverter Transient Characteristicsmentioning

confidence: 81%

“…With remarkable improvement in the device behavior including ultra-low leakage current, higher ON current, nearideal subthreshold swing, lower thermal noise and lower device and interconnect resistance [22], Cryo-CMOS has shown promising results for achieving higher performance and/or obtaining better power efficiency [2], [15]. Design requires well calibrated transistor models for low temperature operation, that can be used for circuit level simulations.…”

Section: Introductionmentioning

confidence: 99%

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Power Performance Analysis of Digital Standard Cells for 28 nm Bulk CMOS at Cryogenic Temperature Using BSIM Models

Saligram

Chakraborty

Cao

et al. 2021

IEEE J. Explor. Solid-State Comput. Devices Circuits

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Cryogenic CMOS is a crucial component in building scalable quantum computers, predominantly for interface and control circuitry. Further, high performance computing can also benefit from cryogenic boosters. This necessitates an in-depth understanding of the power and performance trade-offs in cryogenic operation of digital logic. In this paper, we analyze digital standard cells in 28nm High-K Metal Gate (HKMG) CMOS foundry Process Design Kit (PDK). We have developed BSIM4 models of cryogenic CMOS and calibrated with experimental measurements. Since, low temperature operation leads to an exponential decrease in the leakage current of the transistors, we further tune the threshold voltage of the devices to achieve iso-leakage. In this paper, we present inverter static and dynamic characteristics and multiple Ring Oscillator(RO) structures. The simulation study shows that we can achieve 28%(FO4-RO) -59%(NAND3-RO) higher performance under iso-VDD scenario and up to 90% improvement in the Energy Delay Product (EDP) under isooverdrive scenario at 6K compared to room temperature.

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Section: B Inverter Transient Characteristicsmentioning

confidence: 81%

Section: Introductionmentioning

confidence: 99%

Power Performance Analysis of Digital Standard Cells for 28 nm Bulk CMOS at Cryogenic Temperature Using BSIM Models

Saligram

Chakraborty

Cao

et al. 2021

IEEE J. Explor. Solid-State Comput. Devices Circuits

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“…Sanuki et al [55] and Aiba et al [2] developed 3D flash prototype for cryogenic computing and showed the potential of higher endurance, capacity, and speed-up. Saligram et al [54] showed the characteristics of processors for various cryogenic temperatures and voltages. However, no previous works proposed the novel pipeline and NoC architecture to exploit the fast cryogenic wires.…”

Section: Related Workmentioning

confidence: 99%

CryoWire: wire-driven microarchitecture designs for cryogenic computing

Min

Chung

Byun

et al. 2022

Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

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Cryogenic computing, which runs a computer device at an extremely low temperature, is promising thanks to its significant reduction of wire resistance as well as leakage current. Recent studies on cryogenic computing have focused on various architectural units including the main memory, cache, and CPU core running at 77K. However, little research has been conducted to fully exploit the fast cryogenic wires, even though the slow wires are becoming more serious performance bottleneck in modern processors. In this paper, we propose a CPU microarchitecture which extensively exploits the fast wires at 77K. For this goal, we first introduce our validated cryogenic-performance models for the CPU pipeline and network on chip (NoC), whose performance can be significantly limited by the slow wires. Next, based on the analysis with the models, we architect CryoSP and CryoBus as our pipeline and NoC designs to fully exploit the fast wires. Our evaluation shows that our cryogenic computer equipped with both microarchitectures achieves 3.82 times higher system-level performance compared to the conventional computer system thanks to the 96% higher clock frequency of CryoSP and five times lower NoC latency of CryoBus. CCS CONCEPTS• Computer systems organization → Superscalar architectures; Pipeline computing; Multicore architectures.

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“…Further, the power, delay and reliability of 5nm FinFET SRAM circuits has been studied at deep cryogenic temperatures [6]. A recent theoretical study demonstrated 4× improvement in performance-per-watt at the processor level (Arm Cortex-A53) at cryogenic temperatures [7]. The improvement in performance per watt becomes even better at the system level, where recent study demonstrated 12× at the CPU level and 16× at the system level [8], through circuit and architecture co-optimization.…”

Section: Introductionmentioning

confidence: 99%

“…The improvement in performance per watt becomes even better at the system level, where recent study demonstrated 12× at the CPU level and 16× at the system level [8], through circuit and architecture co-optimization. Furthermore, thermal conductance of silicon increases under cryogenic temperatures, improving the heat dissipation and reducing self-heating effects toward higher integration density [4], [7], [9]. On the other hand, due to the steeper sub-threshold characteristics at cryo-temperatures, the CMOS device becomes highly sensitive to bias voltages and process variations [10].…”

Section: Introductionmentioning

confidence: 99%

Design Exploration of 14 nm FinFET for Energy-Efficient Cryogenic Computing

Gaidhane,

Saligram,

Chakraborty

et al. 2023

IEEE J. Explor. Solid-State Comput. Devices Circuits

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Cryogenic operation of CMOS transistors (i.e., cryo-CMOS) effectively brings an ultra-steep sub-threshold slope and ultra-low leakage, enabling high energy efficiency with appropriate tuning of threshold voltage and supply voltage. On the other hand, cryo-CMOS suffers from elevated sensitivity to process and voltage variations. To facilitate early-stage design exploration, we develop predictive BSIM-CMG model cards, which are calibrated with 14nm TCAD simulation and our experimental FinFET data from 300K to 77K. These models are scalable with temperatures from 300K down to 77K, device engineering and variations. Based on them, we benchmark various circuit examples to illustrate the tremendous potential of cryo-CMOS for energy-efficient computing, in the presence of process variations. For logic circuits, such as a canonical critical path, more than 15× reduction in total energy consumption is demonstrated at 77K for the iso-Delay condition, compared to the operation at the room temperature (RT). The presence of variations only has a marginal impact on energy efficiency, after threshold voltage and supply voltage are adaptively increased. For static noise margin (SNM), it is consistently improved at 77K. However, the impact of variations on SNM is much more pronounced than that on logic circuits.

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A 64-Bit Arm CPU at Cryogenic temperatures: Design Technology Co-Optimization for Power and Performance

Cited by 12 publications

References 0 publications

Power Performance Analysis of Digital Standard Cells for 28 nm Bulk CMOS at Cryogenic Temperature Using BSIM Models

Power Performance Analysis of Digital Standard Cells for 28 nm Bulk CMOS at Cryogenic Temperature Using BSIM Models

CryoWire: wire-driven microarchitecture designs for cryogenic computing

Design Exploration of 14 nm FinFET for Energy-Efficient Cryogenic Computing

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