CryoWire: wire-driven microarchitecture designs for cryogenic computing

Abstract

Cryogenic computing, which runs a computer device at an extremely low temperature, is promising thanks to its significant reduction of wire resistance as well as leakage current. Recent studies on cryogenic computing have focused on various architectural units including the main memory, cache, and CPU core running at 77K. However, little research has been conducted to fully exploit the fast cryogenic wires, even though the slow wires are becoming more serious performance bottleneck in modern processors. In this paper, we propose a CPU microarchitecture which extensively exploits the fast wires at 77K. For this goal, we first introduce our validated cryogenic-performance models for the CPU pipeline and network on chip (NoC), whose performance can be significantly limited by the slow wires. Next, based on the analysis with the models, we architect CryoSP and CryoBus as our pipeline and NoC designs to fully exploit the fast wires. Our evaluation shows that our cryogenic computer equipped with both microarchitectures achieves 3.82 times higher system-level performance compared to the conventional computer system thanks to the 96% higher clock frequency of CryoSP and five times lower NoC latency of CryoBus. CCS CONCEPTS• Computer systems organization → Superscalar architectures; Pipeline computing; Multicore architectures.

Unveiling Enhanced Trade-offs in SRAM-based Memory Arrays for Cryogenic CMOS Technology

“…Cryogenic SRAM are also utilized HP computing systems. Apart from the high-performance core, HP computing systems primarily consist of buffers and SRAM-based caches [8], [9], [25]. These caches are designed at multiple levels to fulfill the timing and area constraints of the HP computing systems.…”

“…Cryogenic computing promises a significant improvement in the performance and power consumption for quantum computing, exascale and high-performance computing, and deep space electronics (Fig. 1) [1]- [3], [7], [8], [10]- [13]. A lower I leak in CMOS transistors and smaller wire resistance at cryogenic temperatures can help to further upscale the clock frequency of the computers under a constant power budget.…”

“…Thus, cryogenic temperature stands as one of the compelling solutions for the realization of efficient memory systems required for exascale computing. Authors in [9] depicted that the overall power consumption of SRAM-based last level cache (LLC) in a CPU running at ∼ 77 K reduces by 50 % compared to 300 K. There has been little exploration of cryogenic caches and memory [8], [9]. Authors in [8] presented the cache optimization at the architecture level.…”

“…Authors in [9] depicted that the overall power consumption of SRAM-based last level cache (LLC) in a CPU running at ∼ 77 K reduces by 50 % compared to 300 K. There has been little exploration of cryogenic caches and memory [8], [9]. Authors in [8] presented the cache optimization at the architecture level. Most of these works were based on the off-the-shelf SRAM array and have not explored the impact of cryogenic temperature to optimize the array size.…”

XQsim

“…SFQ and cryogenic CMOS modeling. Lee et al [41], Byun et al [7], and Min et al [50,51] developed a 77K cryogenic CMOS modeling tool and performed design space exploration for various computer devices including DRAM, cache, and processor. Zokaee et al [73] proposed a 4K CMOS modeling tool for the DRAM.…”