A 60 GHz Power Amplifier in 90nm CMOS Technology

Heydari, Babak; Bohsali, M.; Adabi, Ehsan; Niknejad, Ali M.

doi:10.1109/cicc.2007.4405843

Cited by 28 publications

(16 citation statements)

References 9 publications

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“…g. 19. Block diagram of the 60-GHz transceiver in Fi transmitter, it is possible to implement a gigabit CMOS ansmitter with dc power consumption less than 200 mW tr Based on the 200-mW dc power budget, the output P 1dB of the transmitter is difficult to reach the maximum system output power limit, +10 dBm, unless we can design a high efficiency 60-GHz CMOS PA with 20% [10] or higher PAE or a MMW linearizer [23] for better linearity near saturation power output. The dc power consumption of transmitter blocks is plotted in Fig.…”

Section: A Power Amplifiermentioning

confidence: 99%

Millimeter-wave CMOS integrated circuits for gigabit WPAN applications

Huang

Wang

2008

2008 IEEE Custom Integrated Circuits Conference

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The 60-GHz gigabit wireless personal area network (WPAN) is an attractive application for next-generation dualmode broadband wireless network. The CMOS technologies enable the low-cost manufacturability and system-on-chip (SoC) integration for 60-GHz low-power mobile devices. This paper compares the RF performance of the reported 60-GHz CMOS transceivers, and also discusses the architecture design trade-offs between performances and dc power consumption.

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Section: A Power Amplifiermentioning

confidence: 99%

Millimeter-wave CMOS integrated circuits for gigabit WPAN applications

Huang

Wang

2008

2008 IEEE Custom Integrated Circuits Conference

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“…But for high output power, the total width (W) needs to be large. This means that a large number of fingers need to be placed in parallel; the connections to all these fingers introduce lossy parasitics, reducing gain and efficiency [2].In order to simultaneously optimize the PA and transformers, the following systematic design algorithm is used: (i) An appropriate NMOS device size (W F =1μm, W=80μm in our design) and bias current (22mA) are selected, ensuring that the device is biased near peak f t current density (0.3mA/μm). The contours for constant 1dB compressed output power and power gain (Gp) are then plotted on a Smith chart and an optimum drain load impedance (Z OPT ) is chosen (Fig.…”

mentioning

confidence: 99%

“…However, very few CMOS mmwave power amplifiers (PAs) have been reported so far. Furthermore, most of the mm-wave PAs reported use bulky transmission lines [2,3], increasing silicon area and incurring higher substrate losses.We demonstrate a fully integrated 60GHz transformer-coupled two-stage differential power amplifier with single-ended input and output in 90nm digital CMOS with no RF process options. This work uses on-chip transformers for a 60GHz PA as an integrated CMOS solution.…”

mentioning

confidence: 99%

A 60GHz 1V + 12.3dBm Transformer-Coupled Wideband PA in 90nm CMOS

Chowdhury

Reynaert

Niknejad

2008

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers

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The opening up of the mm-wave band has created opportunities for high-data-rate communication, radar and medical imaging. The cost and size advantages of CMOS have motivated research on 60GHz CMOS front-end design [1]. However, very few CMOS mmwave power amplifiers (PAs) have been reported so far. Furthermore, most of the mm-wave PAs reported use bulky transmission lines [2,3], increasing silicon area and incurring higher substrate losses.We demonstrate a fully integrated 60GHz transformer-coupled two-stage differential power amplifier with single-ended input and output in 90nm digital CMOS with no RF process options. This work uses on-chip transformers for a 60GHz PA as an integrated CMOS solution. Operating from a 1V supply, it achieves a 1dB compressed output power of +9dBm and saturated power of +12.3dBm. The chip occupies an area of only 660×380µm 2 by taking advantage of the extensive use of small transformers.Transformers are attractive as they can simultaneously perform impedance transformation and differential-to-single-ended conversion. In a multistage design, they also provide easy DC biasing. In this design, a 1:1 vertical transformer is built with two coupled loop inductors. The diameter of the loop inductors is an important design metric. For very small sizes, the impedance of the shunt magnetizing inductance becomes too small and most of the signal current is lost through it. A large transformer results in higher substrate losses and an increased series leakage inductance which also reduces the signal transfer to the secondary winding [4].Transformers with different diameters and trace widths have been implemented with the top two metal layers. Figure 31.2.1 shows the simulated minimum insertion loss of 60GHz transformers, clearly indicating how the size can be optimized. Figure 31.2.2 shows the measured insertion loss versus frequency of a vertical transformer with a 42μm diameter and 8μm trace width. At 60GHz, the loss is below 0.9dB, showing the potential of transformers at these frequencies. The measured S 21 shows the broadband nature of transformers, with 3dB bandwidth close to 30GHz.The design of the PA is a simultaneous optimization of output power, power gain and efficiency while ensuring unconditional stability over all frequencies. The implemented circuit is shown in Fig. 31.2.3. It consists of two differential amplifier stages and optimized transformers for input, inter-stage, and output matching and differential-to-single-ended conversion. Note that the use of transformers eliminates the need for AC coupling capacitors and RF chokes while differential operation reduces the amount of bypass capacitance needed.A difference in mm-wave PA design versus lower frequencies is a pronounced limitation on the maximum device width. Choosing the size of the output NMOS transistor is a compromise between maximum stable gain (MSG) and maximum output power. For high gain, the width of a finger (W F ) needs to be small enough. But for high output power, the total width (W) needs to be large. This mean...

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“…Thanks to load pull simulations the output was matched at the optimal load (R opt = 10 Ω) in order to deliver a maximum power at 60GHz. Stability criteria, isolation results are reported in table [1]. Large signal simulations, at 60GHz, were performed in Cadence environment.…”

Section: Circuit Designmentioning

confidence: 99%

“…In the ISM band, a 7GHz unlicensed bandwidth around 60GHz is employed [1] [2] [3] [4]. Communications systems are able to ensure 1-3 GBit/s for directional links using an ASK, PSK modulation, or using an Omni-directional link with OFDM modulation with a rate higher than 500Mbps [5].…”

Section: Introductionmentioning

confidence: 99%

A 60GHz, 13 dBm fully integrated 65nm RF-CMOS power amplifier

Aloui

Kerhervé²,

Belot³

et al. 2008

2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference

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Abstract-A 65nm CMOS, 60GHz fully integrated power amplifier (PA) from STMicroelectronics has been designed for low cost Wireless Personal Area Network (WPAN). It has been optimized to deliver the maximum linear output power (OCP1) without using parallel amplification topology. The simulated OCP1 is equal to 8.9 dBm with a gain of 8dB. To obtain good performances and consume an ultra compact area of silicon, the PA has been matched and optimized with a mixed technique, using lumped and distributed elements. The chip size is 0.48mm*0.6mm including pads.

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A 60 GHz Power Amplifier in 90nm CMOS Technology

Cited by 28 publications

References 9 publications

Millimeter-wave CMOS integrated circuits for gigabit WPAN applications

Millimeter-wave CMOS integrated circuits for gigabit WPAN applications

A 60GHz 1V + 12.3dBm Transformer-Coupled Wideband PA in 90nm CMOS

A 60GHz, 13 dBm fully integrated 65nm RF-CMOS power amplifier

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