A 60GHz, 13 dBm fully integrated 65nm RF-CMOS power amplifier

Aloui, Sofiane; Kerhervé, Eric; Belot, Didier; Plana, R.

doi:10.1109/newcas.2008.4606365

Cited by 6 publications

(2 citation statements)

References 10 publications

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“…Nevertheless, design of efficient CMOS PAs remains challenging because of low gain of transistors at these frequencies, low breakdown voltage of CMOS transistors and losses of on-chip passive power combiners in deep sub-micron CMOS process [1]. To date, there have been several CMOS PAs targeting high gain and output power at 60 GHz [2]- [11]. Considering the fact that the gain of the power MOSFETs with large channel width is relatively low at mmW frequencies, a single-stage PA cannot deliver a high gain and high power simultaneously [3].…”

Section: Introductionmentioning

confidence: 99%

Compact high-power 60 GHz power amplifier in 65 nm CMOS

Farahabadi

Moez

2013

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference

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This paper presents a compact 60 GHz power amplifier utilizing a novel 4-way multi-conductor power combiner and splitter. The proposed topology provides the capability of combining the output power of four individual power amplifier cores in a compact die area of 0.025 mm 2 with the advantage of lower insertion loss and higher efficiency compared to the conventional distributed active transformer topology. Each power amplifier core consists of a three-stage common-source amplifier with transformer-coupled impedance matching networks. Fabricated in 65 nm CMOS process, the measured gain of the 0.19 mm 2 power amplifier is 18.8 dB at 60 GHz with 3dB band width of 4 GHz while consuming 424 mW from a 1.4V supply. A maximum saturated output power of 18.3dBm is measured with the 15.9% peak power added efficiency at 60 GHz.

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Section: Introductionmentioning

confidence: 99%

Compact high-power 60 GHz power amplifier in 65 nm CMOS

Farahabadi

Moez

2013

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference

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“…Power amplifier designers often rely on RF power simulations using compact device models [1][2]. These simulations are very time consuming and the need for accurate compact models means that the power estimations are only accurate when designing in mature device technologies.…”

Section: Introductionmentioning

confidence: 99%

Analytical model for RF power performance of deeply scaled CMOS devices

Gogineni

Alamo

Valdes‐Garcia

2011

2011 IEEE Radio Frequency Integrated Circuits Symposium

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-This paper presents a first order model for RF power of deeply scaled CMOS. The model highlights the role of device on-resistance in determining the maximum RF power. We show excellent agreement between the model and the measured data on 45 nm CMOS devices across a wide range of device widths, under both maximum output power and maximum PAE conditions. The model allows circuit designers to quickly estimate the power and efficiency of a device layout without need for complicated compact models or simulations.

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Design of a 2 Gb/s transceiver at 60 GHz with integrated antenna in bulk CMOS technology

Saponara

Mattii

Neri

et al. 2014

2014 9th European Microwave Integrated Circuit Conference

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This work presents the design of a 60 GHz OOK transceiver, with on-chip integrated antenna, for multi Gbit short -range wireless communication. A 65 nm bulk CMOS technology has been selected as target to prove that high-speed fully-integrated RF transceivers can be realized also with low cost digital technologies, suited for wireless consumer applications. The OOK modulation scheme allows for low complex transceiver architecture with all passive and active devices integrated on-chip. At TX side the power stage combines two class-A power amplifiers in a pseudo differential scheme, each made up of a 2 stage Common Source topology with a G(T) gain of 6.8 dB and a OP1dB of 8.2 dBm. The whole transmitter allows for an output power of about 11 dBm. The antenna is integrated on-chip adopting an half-wavelength dipole topology. Simulated results are a radiation efficiency of 38% and a gain of -1.76 dBi. At RX side a single-stage cascode LNA with a G(T) gain of 11.46 dB and a noise figure (NF) of 4.69 dB is followed by an OOK demodulator realized with a simple envelope detector. Since both antenna and LNA are integrated on-chip, the impedance matching is not constrained to a 50 Omega value, but its value can be tuned to find an optimal trade-off between NF and gain of the receiver. Combining the proposed RF transceiver with the use of Reed-Solomon channel coding in the digital baseband a data link with an effective data rate of 2 Gb/s can be implemented; the BER is less than 10(-5) and 10(-12) at 2 m and 1.1 m distance respectivel

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A 60GHz, 13 dBm fully integrated 65nm RF-CMOS power amplifier

Cited by 6 publications

References 10 publications

Compact high-power 60 GHz power amplifier in 65 nm CMOS

Compact high-power 60 GHz power amplifier in 65 nm CMOS

Analytical model for RF power performance of deeply scaled CMOS devices

Design of a 2 Gb/s transceiver at 60 GHz with integrated antenna in bulk CMOS technology

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