A 60 GHz CMOS power amplifier with modified pre-distortion linearizer

Hsu, Yu-Chung; Kao, Kun-Yao; Kao, Jui-Chih; Tsai, T. C.; Lin, Kun-You

doi:10.1109/mwsym.2013.6697359

Cited by 5 publications

(2 citation statements)

References 13 publications

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“…In cold-mode MOS transistor has been used for MMW PA. It is a built-in linearization technology, which uses its nonlinear distortion characteristics to achieve addition compensation [4] . In order to meet the requirements of high linearity and improve the output 1dB compression point of output power, analog predistortion is a good choice.…”

Section: Introductionmentioning

confidence: 99%

A 28GHz Power Amplifier with Analog Predistortion Linearizer in 65nm CMOS

Dou

2021

JERA

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This paper proposes that a radio frequency power amplifier is suitable for a 5G millimeter wave. It adopts a three-stage single-ended structure at 28GHz. An analog predistortion linearization method is used to improve the linearity of the power amplifier (PA). As a result, there is a significant improvement in power-added efficiency (PAE) and linearity is achieved. The Ka-band PA is implemented in TSMC 65nm CMOS process. At 1.2V supply voltage, the PA proposed in this paper achieves a saturated output power of 15.9dBm and a PAE of 16%. After linearization, the output power at the 1dB compression point is increased by 2dBm, with efficient gain compensation performance.

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Section: Introductionmentioning

confidence: 99%

A 28GHz Power Amplifier with Analog Predistortion Linearizer in 65nm CMOS

Dou

2021

JERA

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“…Low breakdown voltage and high substrate loss also interrupt the performance of power efficiency and output power [10,11]. To demonstrate high PAE and low power consumption can be achieve simultaneously for a 28 GHz CMOS PA, in this work, we report a 28 GHz PA with excellent PAE, Psat and low power consumption properties using 0.18 µm Siltera process technology.…”

Section: Introductionmentioning

confidence: 99%

A 28 GHz high efficiency fully integrated 0.18 µm combined CMOS power amplifier using power divider technique for 5G millimeter-wave applications

Hasan¹,

Murad²,

Bakar³

et al. 2020

Bulletin EEI

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A 28 GHz power amplifier (PA) using CMOS 0.18 µm Silterra process technology for milimeter wave applications is reported. Maximizing the power added efficiency (PAE) and output power are achieved by optimize the circuit with power divider and cascade configuration. In addition, reverse body bias is also employed for realizing excellent PAE and power consumption. A three stage CMOS PA with power combiner is designed and simulated. The simulation results show that the proposed PA consumes 62.56 mW and power gain (S21) of 8.08 dB is achieved at 28 GHz. The PA achieves saturated power (Psat) of 12.62 dBm and maximum PAE of 23.74% with output 1-dB compression point (OP1dB) 10.85 dBm. These results demonstrate the proposed power amplifier architecture is suitable for 5G applications.

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A Dual-Mode Wideband +17.7-dBm 60-GHz Power Amplifier in 65-nm CMOS

Farahabadi

Moez

2017

IEEE Trans. Compon., Packag. Manufact. Technol.

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A 60 GHz CMOS power amplifier with modified pre-distortion linearizer

Cited by 5 publications

References 13 publications

A 28GHz Power Amplifier with Analog Predistortion Linearizer in 65nm CMOS

A 28GHz Power Amplifier with Analog Predistortion Linearizer in 65nm CMOS

A 28 GHz high efficiency fully integrated 0.18 µm combined CMOS power amplifier using power divider technique for 5G millimeter-wave applications

A Dual-Mode Wideband +17.7-dBm 60-GHz Power Amplifier in 65-nm CMOS

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