This article presents 75‐110‐GHz highly isolated T/R switch in 90nm CMOS. The proposed T/R switch circuit design is focused on highly isolation performance which is achieved by using both parallel inductors and leakage‐cancellation techniques. To also reduce insertion loss which is also an important design key point, series‐shunt single‐pole double throw (SPDT) switch with optimizing transistors size and body‐floating technique are adopted. From the experiment results, the designed switch has good performance of the return loss, insertion loss and isolation in W‐band. Compared with some previously reported works, the designed switch has the best isolation performance of 48 dB at 94‐GHz, and IP1dB is > 9dBm, respectively.© 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:2725–2731, 2016