A 5GS/s 10b 76mW time-interleaved SAR ADC in 28nm CMOS

Fang, Jie; Thirunakkarasu, Shankar; Yu, Xuefeng; Silva-Rivas, Fabian; Kim, Kwang Young; Zhang, Chaoming; Singor, Frank

doi:10.1109/cicc.2015.7338385

Cited by 10 publications

(3 citation statements)

References 4 publications

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“…When the sampling rate is 1 Gsps,the SNR of the acquisition system developed by Gupta et al is only 57.8 dB when the input frequency is 400 MHz 29 . In addition, when the input frequency is 1 GHz or 400 MHz, the SNR of the acquisition reported in other literatures are generally lower than 60 dB 30‐35 …”

Section: The Experiments and Conclusionmentioning

confidence: 92%

“…29 In addition, when the input frequency is 1 GHz or 400 MHz, the SNR of the acquisition reported in other literatures are generally lower than 60 dB. [30][31][32][33][34][35] It clearly shows that the clock system we designed with the characteristics of high precision and low jitter, would greatly improve the SNR characteristics of the acquisition system.…”

Section: Analysis For Sampled Datamentioning

confidence: 93%

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A generation and distribution system of clock signal source for signal acquisition system

Zhang

Shang

et al. 2021

Engineering Reports

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The clock signal is the heartbeat of modern electronic system, and demands of increasing high-quality signal has been raised, with the development of science and technology in the field of electronic information. The clock signal with low jitter is helpful to improve the signal-to-noise ratio (SNR) of sampled data and obtain high-precision result. In this article, a programmable clock system of signal generation and distribution is designed for high-speed acquisition system.The system can provide the clock of low jitter which frequency is as high as 3.2 GHz. The output channels for clock are 14 and each channel for clock can also be configured for synchronizing, delay adjusting or calibrating. Based on the system, a new type of configuration program is developed by using Verilog language. It can directly control the chip which has better compatibility in the application scenario of Field Programmable Gate Array (FPGA) as the master chip. It also provides a reference and guidance for the design and implementation of the dual-Phase Locked Loop clock chips. When it provides the clocks for the high-speed acquisition system, the SNR of the acquisition signal has been significantly improved compared with similar acquisition systems. It indicates that the clock system we designed provides an effective way for the high-speed acquisition system to obtain the data with higher SNR.

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Section: The Experiments and Conclusionmentioning

confidence: 92%

Section: Analysis For Sampled Datamentioning

confidence: 93%

A generation and distribution system of clock signal source for signal acquisition system

Zhang

Shang

et al. 2021

Engineering Reports

View full text Add to dashboard Cite

show abstract

“…Timing-skew calibration is a critical topic for higher and higher input frequency. Several calibration methods has been proposed [1][2] [3] but they usually implement in digital domain and complicated digital circuit or filter is required, occupying large area and power For offset and gain calibration, it is easy to perform calibration in digital domain [4], but it needs large amount of registers and arithmetic logic units which is another overhead to power and area. As for analog domain, input shorting detection [5] has been widely adopted to detect offset's polarity, but gain calibration is usually hard to perform in analog domain.…”

Section: Introductionmentioning

confidence: 99%

A 1.6-GS/s 8b Flash-SAR Time-Interleaved ADC with Top-Plate Residue Based Gain Calibration

Hsu

Chang

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper presents a 4-channel 8-bit 1.6-GS/s Flash assisted SAR Time-Interleaved ADC in 40-nm CMOS. Putting all channel mismatch including offset, gain and timingskew into consideration. Modified bootstrap circuit used to inhibit timing-skew; background offset calibration without complicated circuit performed in the analog domain. Proposed background gain calibration detects signal which correlated with gain error in SAR ADC and correct gain mismatch by simple calibration capacitor array, which only increase a little power and area overhead. Hybrid architecture has been adopted in this chip. Owing to Flash-SAR operation, single channel's speed and overall energy efficient can be promote at the same time. The calibration enhance SNDR from 34.59-dB to 44.15-dB. Moreover, this design consumes 16.76mW under 1V supply with FoM of 78.93fJ/conv-step in the measurement.

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