A 55nm Ultra Low Leakage Deeply Depleted Channel technology optimized for energy minimization in subthreshold SRAM and logic

Patel, Harsh; Roy, Abhishek; Yahya, Farah B.; Liu, Ningxi; Calhoun, Benton H.; Kumeno, Kazuyuki; Yasuda, Makoto; Harada, Ayako; Ema, T.

doi:10.1109/essderc.2016.7599583

Cited by 4 publications

(11 citation statements)

References 16 publications

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“…However, with ULL DDC devices, the V th degradation with a thicker gate dielectric is relaxed by 60% compared to the conventional device at the same gate dielectric thickness as shown in Figure 5.10. Figure 5.11 shows the TEM representation of a 55nm ULL Figure 5.10: Impact of increase in Gate-Oxide (T OX ) on V th variation [11] device in DDC technology. The un-doped channel and highly doped screen layer reduce V th variation in DDC [78].…”

Section: Ddc Technologymentioning

confidence: 99%

“…The ULL device using DDC further reduces leakage using an optimal selection of channel lengths combined with body biasing. Figure 5 [11] design optimization. ULL DCC is an attractive technology to address the two most pressing challenges for sub-µW systems: 1) reduced drive strength, and 2) lower yield due to V th variation.…”

Section: Ddc Technologymentioning

confidence: 99%

“…Major contributing leakage currents[11] µ = mobility of carriersC ox = gate oxide capacitance per unit area (W/L) = device aspect ratio η = capacitive coupling between the gate and silicon surface V T = thermal voltage As shown in Equation 5.1, the source-to-body biasing (V SB ) controls the threshold voltage (V th ) [82][83]. The device is reverse body biased (RBB) by applying a negative voltage to the bulk in the case of NMOS and applying > VDD voltage to the bulk of the PMOS to increase the V th .…”

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confidence: 99%

“…However, the lightly doped n and p regions in DDC ULL devices help to attenuate Band-to-Band Tunneling (BTBT) dominating the p-n junction leakage.Figure 5.16shows measured sub-threshold leakage and junction leakage at varying degrees of RBB and a corresponding increase in the junction current (I junc ) and decrease in sub-threshold leakage (I sub ). Across VDD, varying degrees of RBB results in I ON degradation with increasing degree of RBB[11]…”

mentioning

confidence: 99%

“…18 shows a die photo of the fabricated chip in DDC technology Effective leakage reduction using RBB − Increasing degree of RBB reduces sub-threshold leakage ∼100X while increases junction current increases by less than 10X across supply voltages[11] Ultra low power detection circuits in wakeup receiver systemsEvent driven wake-up receivers form an integral component in emerging remote IoE sensing applications. This has become a major driving force for researchers to develop sensor nodes operating under stringent power consumption limits in the order of several nano-Watts.…”

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Power Management in Ultra-Low Power Systems

Roy¹

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The evolving vision of the Internet-of-Things (IoT) will revolutionize various applications such as remote health monitoring, home automation and remote surveillance. It has been projected that by 2025, there will be 1 trillion IoT devices influencing our daily lives. This will result in the generation of an enormous amount of data, which will have to be stored, processed and transmitted efficiently and reliably. Although advancements in Integrated Circuit (IC) design and the availability of various Ultra-low Power (ULP) circuit components have helped us to visualize an ecosystem of numerous internet-connected devices, the overall system integration will become a major challenge. A System-on-Chip (SoC), catering to IoT applications is expected to contain many different circuit components such as sensors and Analog-Front-Ends (AFEs) for real-time signal acquisition, analog-to-digital converters, digital signal processors, memories, wireless transceivers etc. All these components have different supply voltage requirements and power profiles. Hence, power delivery to such components in an SoC will play an important role in the overall system architecture. Although, battery-powered systems have traditionally worked well in portable electronics but in an IoT ecosystem, the cost of battery replacement in a trillion-sensor node network will be enormous. In many applications, such as remote surveillance, systems require a long operational lifetime. Moreover, system deployment should be unobtrusive and hence such systems should have small form factors.The above requirements are hard to meet using conventional battery-powered systems. Hence, in most IoT SoCs, there is a strong motivation for an integrated Power Management Unit (PMU), with energy harvesting capability for near-perpetual battery-less operation, which i Abstract ii can provide a range of supply voltage rails to satisfy the electrical specifications of different functional units.This dissertation addresses the design challenges related to energy autonomy and powerdelivery in a wireless sensor node. This work presents an energy harvesting platform in context of a self-powered System-in-Package (SiP) with a capability to harvest from either photovoltaic or thermoelectric generators (TEGs). The SiP consists of an SoC for processing and storage, non-volatile memory, a wireless transceiver and various off-the-shelf sensors. To deliver power and to meet the electrical specifications of these different components of the sensor node, this work presents an efficient, low quiescent power, supply-voltage regulation scheme. In addition to power delivery, this dissertation also demonstrates several ULP digital and mixed-signal circuit components, commonly used in energy-autonomous and always-ON systems such as an event-driven wakeup receiver. This work describes circuit solutions and techniques related to power delivery that will enhance the operational lifetime, reduce the overall form-factor and contribute towards attaining energy-autonomy to facilitate a wide range of a...

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Section: Ddc Technologymentioning

confidence: 99%

Section: Ddc Technologymentioning

confidence: 99%

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confidence: 99%

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confidence: 99%

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Power Management in Ultra-Low Power Systems

Roy¹

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Performance of Power Converters for Ultra Low Power Systems: A Review

George

Kulkarni

2018

2018 Second International Conference on Advances in Electronics, Computers and Communications (ICAECC)

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A Construction Kit for Efficient Low Power Neural Network Accelerator Designs

Jokic¹,

Azarkhish²,

Bonetti³

et al. 2022

ACM Trans. Embed. Comput. Syst.

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Implementing embedded neural network processing at the edge requires efficient hardware acceleration that combines high computational throughput with low power consumption. Driven by the rapid evolution of network architectures and their algorithmic features, accelerator designs are constantly being adapted to support the improved functionalities. Hardware designers can refer to a myriad of accelerator implementations in the literature to evaluate and compare hardware design choices. However, the sheer number of publications and their diverse optimization directions hinder an effective assessment. Existing surveys provide an overview of these works but are often limited to system-level and benchmark-specific performance metrics, making it difficult to quantitatively compare the individual effects of each utilized optimization technique. This complicates the evaluation of optimizations for new accelerator designs, slowing-down the research progress. In contrast to previous surveys, this work provides a quantitative overview of neural network accelerator optimization approaches that have been used in recent works and reports their individual effects on edge processing performance. The list of optimizations and their quantitative effects are presented as a construction kit, allowing to assess the design choices for each building block individually. Reported optimizations range from up to 10’000x memory savings to 33x energy reductions, providing chip designers an overview of design choices for implementing efficient low power neural network accelerators.

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A 55nm Ultra Low Leakage Deeply Depleted Channel technology optimized for energy minimization in subthreshold SRAM and logic

Cited by 4 publications

References 16 publications

Power Management in Ultra-Low Power Systems

Power Management in Ultra-Low Power Systems

Performance of Power Converters for Ultra Low Power Systems: A Review

A Construction Kit for Efficient Low Power Neural Network Accelerator Designs

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