A 55-nm, 0.86-Volt operation, 75MHz high speed, 96uA/MHz low power, wide voltage supply range 2M-bit split-gate embedded Flash

Cho, C. Y.-S; Wang, J. C.; Huang, Long; Weng, Ming Hung; Lin, Yung-Tao; Lee, C. F.; Lien, Chiu-Wang; Feng, Haonan; Yang, Tao; Liao, Scott; Wu, J. J.; Chih, Yu-Der; Natarajan, S.

doi:10.1109/vldi-dat.2013.6533877

Cited by 3 publications

(1 citation statement)

References 7 publications

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“…We show the published cell size for all technologies discussed above in figure 1(c), i.e. SRAM [46][47][48][49][50][51][52][53], eDRAM [54][55][56][57][58][59], eFlash [60][61][62][63][64][65][66][67], DRAM [41,68], eReRAM [69][70][71][72][73], STT-MRAM [42,[74][75][76][77][78][79][80][81][82][83][84][85][86][87]. Note that the SRAM cell sizes down to 7 nm are from literature while the cell sizes (F 2 ) for 3 and 5 nm are linear extrapolation based on the cell sizes from 22 nm to 7 nm.…”

Section: Scaling Analysismentioning

confidence: 99%

Voltage-controlled magnetic tunnel junctions with synthetic ferromagnet free layer sandwiched by asymmetric double MgO barriers

Grèzes

Wong

et al. 2019

J. Phys. D: Appl. Phys.

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Memory and computing applications utilizing voltage-controlled magnetic random-access memory (MRAM) require perpendicular magnetic tunnel junctions (pMTJs) capable of high thermal stability and large write efficiency at advanced technology nodes. We first discuss the scaling requirements for voltage-controlled MRAM to replace various existing memory applications at an advanced CMOS technology node, including cell size, thermal stability, interfacial perpendicular magnetic anisotropy (PMA), and voltage-controlled magnetic anisotropy (VCMA). For replacing volatile memories including SRAM, eDRAM, and DRAM, we employ the retention relaxation technique along with a DRAM-style refresh scheme in the analysis. To enhance both PMA and VCMA at scaled nodes, we explore pMTJs with asymmetric double MgO barriers sandwiching a synthetic ferromagnet (SyF) free layer. In a thin MgO/SyF free layer/thick MgO/fixed layer MTJ stack, the SyF free layer is realized in various ways: single layer (X = Ta, W, Mo, Ir) and bilayers (X = Ta/W, Mo/Ir) of heavy metals insertions in CoFeB/X/CoFeB and Co2FeAl/X/Co2FeAl structures, and multiple insertions in [CoFeB/X]n/CoFeB structures for n = 1–4. A VCMA coefficient of 36 fJ (V m)−1 is achieved in a MgO/CoFeB/Ta/CoFeB/MgO-based MTJ which is comparable to that of the single MgO barrier MTJ. We find PMA enhancement, although with VCMA reduction for an increasing number n of [CoFeB/X]n repetitions. In addition, we demonstrate large TMR of 78%, large interfacial PMA of 1.45 mJ m−2, and VCMA of 65 fJ (V m)−1 in a MgO/Co2FeAl/W/Co2FeAl/MgO-based MTJ annealed above 400 °C.

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Section: Scaling Analysismentioning

confidence: 99%

Voltage-controlled magnetic tunnel junctions with synthetic ferromagnet free layer sandwiched by asymmetric double MgO barriers

Grèzes

Wong

et al. 2019

J. Phys. D: Appl. Phys.

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A 55-nm, 0.86-Volt operation, 125MHz high speed, 75uA/MHz low power, wide voltage supply range 2M-bit split-gate embedded Flash

Cho

Wang

Lin

et al. 2013

2013 5th IEEE International Memory Workshop

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A 45-nm logic compatible 4Mb-split-gate embedded flash with 1M-cycling-endurance

Lee

Seo

et al. 2014

2014 IEEE 6th International Memory Workshop (IMW)

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For the first time, 4Mb split-gate type embedded flash is developed in 45-nm technology with 1M cycling endurance for mass production of various applications. Process integration is designed for logic compatibility, minimizing shift of logic device characteristics so that existing IPs can be used. By process optimization of triplegate flash architecture, high speed operation (write time of 25us and erase operation of less than 2ms) and robust reliability (1M cycle, 150 retention) are achieved.

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A 55-nm, 0.86-Volt operation, 75MHz high speed, 96uA/MHz low power, wide voltage supply range 2M-bit split-gate embedded Flash

Cited by 3 publications

References 7 publications

Voltage-controlled magnetic tunnel junctions with synthetic ferromagnet free layer sandwiched by asymmetric double MgO barriers

Voltage-controlled magnetic tunnel junctions with synthetic ferromagnet free layer sandwiched by asymmetric double MgO barriers

A 55-nm, 0.86-Volt operation, 125MHz high speed, 75uA/MHz low power, wide voltage supply range 2M-bit split-gate embedded Flash

A 45-nm logic compatible 4Mb-split-gate embedded flash with 1M-cycling-endurance

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