A 512-Mb DDR3 SDRAM Prototype With<tex>$C_IO$</tex>Minimization and Self-Calibration Techniques

A digital phase corrector with a duty cycle detector and transmitter for a Quad Data Rate I/O scheme

“…Then the differential phase corrector for the ICLK (CLKT[0] and CLKT [2] ), DCCI, is controlled so that the OTX REP differential signal has the duty cycle of 50%. In the second phase correction process, the data pattern of "0110" for REP DAT [3:0] signal is used to detect the phase error between CLKT [1] and CLKT [3]. In this case, DCCQ is controlled by the digital control code supplied from the Register.…”

“…In this case, DCCQ is controlled by the digital control code supplied from the Register. In the last phase correction process, the quadruple phase error between CLKT[0] and CLKT [1] is detected by using the data pattern of "1010" for the REP DAT [3:0] signal. QPCI and QPCQ are simultaneously controlled by the complementary digital code for the quadruple phase relationship between the ICLK and QCLK.…”

“…Thus, the multi-phase clock scheme utilizing a multi-phase clock generator, such as a phase locked loop (PLL) or delay locked loop (DLL), and multiplexers/de-multiplexers is used to reduce the power consumption of the clock signal in a high speed interface [1,2]. Actually, the synchronous dynamic random access memory (SDRAM) reported in the literature [3] adopted a quad data rate (QDR) I/O scheme which used a multi-phase PLL for a 1.45 GHz 4-phase clock and 4-to-1 multiplexers/demultiplexers for data and clock signals.…”

“…The ideal phases of four clocks (CLKT [2] and between CLKT [1] and CLKT [3] have the differential relations and thus are achieved by the duty cycle correction. Then, the phase error correction between ICLK (CLKT[0], CLKT [2] ) and QCLK (CLKT [1], CLKT [3] ) is achieved by the quadruple phase correction.…”

“…Then, the phase error correction between ICLK (CLKT[0], CLKT [2] ) and QCLK (CLKT [1], CLKT [3] ) is achieved by the quadruple phase correction. Hence two duty cycle correction processes and one quadruple phase correction process are required for the phase-error correction of a 4-phase clock.…”