A digital phase corrector with a duty cycle detector and transmitter for a Quad Data Rate I/O scheme

Abstract

Abstract:A digital phase corrector is proposed to reduce the time jitter noise in a high speed parallel chip-to-chip interface system with a quad data rate (QDR) input/output (I/O) scheme. The proposed digital phase corrector for the 4-phase clock utilizes only one duty cycle detector by using a digitally controlled phase correction method and multiplexing function of transmitter for a QDR I/O scheme. Also, it reduces the static phase error generated in the transmitter, because of the inclusion of a replica of the transmitter in the feedback loop. To verify the proposed digital phase correction scheme, a digital phase corrector for the QDR I/O scheme with a 1.25 GHz 4-phase clock was designed by using a 70 nm 3-metal CMOS process with a 1.35 V supply. The current consumption and phase correction range were 2.73 mA and ±8%, respectively.

A 0.8–3.4 GHz process variation insensitive duty-cycle corrector for high-speed memory I/O links

“…To eliminate the clock duty-cycle errors in memory interface channels, input clock buffers, and on-chip clock trees, typical high-speed DRAM and memory controllers utilize analog-type, digital-type or hybrid-type duty-cycle corrector (DCC) circuits [1,2,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20]. The DCCs in DDR3, DDR4, LPDDR4, LPDDR5, and GDDR5 SDRAM applications performs duty-cycle error compensation of high-speed signal pins for a differential clock (CK/CKb), data signals (DQs), and a data strobe signal (DQS).…”

“…Simulated linear duty cycle correction capability of the proposed PFDE according to the V ctrl voltage at 3.4 GHz Layout of the proposed full-swing DCC core IEICE Electronics Express, Vol 16,. No.19,[1][2][3][4][5] …”