A 51.2 GOPS scalable video recognition processor for intelligent cruise control based on a linear array of 128 4-way VLIW processing elements

Kyo, S.; Koga, T.; Okazaki, S.; Uchida, R.; Yoshimoto, S.; Kuroda, I.

doi:10.1109/isscc.2003.1234202

Cited by 28 publications

(25 citation statements)

References 2 publications

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“…This is discussed in more detail in Section 4, which presents the coprocessor architectures. Compared to [4] and [5], this core is low-cost, lowpower and targets a wide application area unlike [6] that is optimized for a single application. Furthermore our solution has built-in logic to work on image segments (i.e ROIs) instead of complete images, something not present in these other solutions.…”

Section: Architecture and Mappingmentioning

confidence: 99%

Design, synthesis and verification of a smart imaging core using SystemC

Kruijtzer

Reyes

Gehrke

2005

Des Autom Embed Syst

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In this paper the development of a smart imaging core following a SystemC-based design flow is presented. The smart imaging core integrates an ARM processor and two specific hardware blocks for image processing: a smart imaging coprocessor and a motion estimation coprocessor. A SystemC-based design flow is applied, comprising the design, synthesis and verification and synthesis of the two coprocessors, as well as the development and integration of the embedded software on the smart imaging core. The two coprocessors are successfully modeled and refined from C/C++-based algorithmic descriptions down to architecture reference models using SystemC and TLM concepts. For the RTL implementation of the coprocessor hardware high-level synthesis tools are used. The applied SystemC-based design flow enabled the iterative refinement of the architecture towards an optimal RTL implementation. Furthermore, the use of SystemC TLM supports the integration of fast functional models of the coprocessors on a virtual prototype platform of the target architecture. This virtual prototype is beneficially used during the embedded software development phase.

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Section: Architecture and Mappingmentioning

confidence: 99%

Design, synthesis and verification of a smart imaging core using SystemC

Kruijtzer

Reyes

Gehrke

2005

Des Autom Embed Syst

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“…2) Feature processor eliminates the throughput bottleneck and increases throughput 36%. 3) The 205GOPS/W power efficiency is 5× better than previous works [2,3] and is achieved by introducing a feature processor, a gatedclock scheme and by reducing memory accesses. and decision processor (DP).…”

mentioning

confidence: 93%

“…However, the precision loss of analog signal processing prevents those solutions from realizing complex algorithms, and they lack flexibility. Vision processors [2,3] realize high GOPS numbers by combining a processor array for parallel operations and a decision processor for other ones. Converting from parallel data in the processor array to scalar in the decision processor creates a throughput bottleneck.…”

mentioning

confidence: 99%

iVisual: An Intelligent Visual Sensor SoC With 2790 fps CMOS Image Sensor and 205 GOPS/W Vision Processor

Cheng

Lin

et al. 2009

IEEE J. Solid-State Circuits

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Visual sensors combined with video analysis algorithms can enhance applications in surveillance, healthcare, intelligent vehicle control, human-machine interfaces, etc. Hardware solutions exist for video analysis. Analog on-sensor processing solutions [1] feature image sensor integration. However, the precision loss of analog signal processing prevents those solutions from realizing complex algorithms, and they lack flexibility. Vision processors [2,3] realize high GOPS numbers by combining a processor array for parallel operations and a decision processor for other ones. Converting from parallel data in the processor array to scalar in the decision processor creates a throughput bottleneck. Parallel memory accesses also lead to high power consumption. Privacy is a critical issue in setting up visual sensors because of the danger of revealing video data from image sensors or processors. These issues exist with the above solutions because inputting or outputting video data is inevitable.iVisual is characterized as follows: 1) Privacy is protected by integrating 2790fps CMOS Image Sensor, 76.8GOPS vision processor and 1Mb storage. It is a light-in-answer-out SoC, and no video data need to be revealed outside the chip. 2) Feature processor eliminates the throughput bottleneck and increases throughput 36%. 3) The 205GOPS/W power efficiency is 5× better than previous works [2,3] and is achieved by introducing a feature processor, a gatedclock scheme and by reducing memory accesses. and decision processor (DP). GP is a parallel data in, parallel data out processor and controls the bitplane memory. FP is a parallel data-in, scalar-out processor and therefore eliminates the throughput bottleneck of data conversion. The DP processes scalar-in, scalar-out operations, that are usually decision results that further control the program execution of the GP and FP.The CIS is frame-pipelined with GP, FP and DP to increase hardware utilization. The port of bitplane memory is shared by CIS and GP; port collision is automatically handled. The port sharing of bitplane memory reduces SRAM area 64% and die area 16% with average collision probability below 0.1%. GP, FP and DP work concurrently. For each instruction, the availability of required resources is checked, including resources in other processors. An instruction will be executed only when all required resources are available. This simple scheme ensures minimum inter-processor communication to synchronize the three processors and increases throughput 23% compared with tightly-coupled processors [2]. The clocks of unused resources are turned off to reduce power. The GP execution unit is a SIMD processor array with 128 processing elements (PEs). The PE cache lies between the PE array and bitplane memory to reduce memory access 94%, saving 726mW of power. The PE cache itself consumes 134mW. Various bitplane memory access patterns and storage allocation schemes are provided to reduce the program size and increase storage density. To enhance flexibility, each PE is indexed and has...

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“…Even though few previous object recognition processor implementations are reported in [19][20][21], they are all targeted for vehicular application having much relaxed power constraints. To the date, there is no dedicated processor implementation which provides sufficient performance for the SIFT computation with low-power consumption.…”

Section: Introductionmentioning

confidence: 99%

Vision platform for mobile intelligent robot based on 81.6 GOPS object recognition processor

Kim

et al. 2008

Proceedings of the 45th Annual Design Automation Conference

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To enable power-efficient object recognition of mobile intelligent robots, 81.6GOPS object recognition processor is proposed. Based on analysis of Scale Invariant Feature Transform (SIFT) algorithm, architecture of the proposed processor is designed to support both task and data level parallelism. 10 Processing Elements (PEs) are integrated for task parallelism, and each PE is equipped with SIMD instruction for data parallelism as well. In addition, Visual Image Processing memory replaces complex local maximum pixel search operation with a single read operation for further performance gain. With the proposed processor, we also realized vision platform for real-time SIFT computation of mobile robots. The chip operation is tested up to 200MHz and consumes 540mW in the vision platform at 1.8V supply voltage and 100 MHz operation frequency.

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A 51.2 GOPS scalable video recognition processor for intelligent cruise control based on a linear array of 128 4-way VLIW processing elements

Cited by 28 publications

References 2 publications

Design, synthesis and verification of a smart imaging core using SystemC

Design, synthesis and verification of a smart imaging core using SystemC

iVisual: An Intelligent Visual Sensor SoC With 2790 fps CMOS Image Sensor and 205 GOPS/W Vision Processor

Vision platform for mobile intelligent robot based on 81.6 GOPS object recognition processor

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