A 50V input range 14bit 250kS/s ADC with 97.8dB SFDR and 80.2dB SNR

Özkaya, İlter; Gürleyük, Çağrı; Ergül, Atılım; Akkaya, Arda; Aksin, Devrim Yılmaz

doi:10.1109/esscirc.2014.6942024

Cited by 9 publications

(4 citation statements)

References 5 publications

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“…The capacitive DAC has been implemented with a BWA topology [15]. This architecture is commonly used for resolutions larger than 10 bits [7,11] for sake of compactness and to reduce layout complexity, since the capacitive banks corresponding to the most-significant bits are built with a smaller number of unit elements than in the conventional binary-weighted (CBW) array. The attenuation capacitor, C att , splits the array into two binary weighted sub-arrays: a main-DAC and a sub-DAC (see Fig.…”

Section: Array Structurementioning

confidence: 99%

“…3). Such radial gradients have already been addressed as a realistic source of non-linearity in [11,12] but no specific layout geometry has been proposed to mitigate their effect. Thus, for high-resolution converters, the proper sizing of the unit capacitor according to Eq.…”

Section: Non-linearity In Capacitive Dacsmentioning

confidence: 99%

“…This issue is exacerbated in CMOS processes like 250-or 350-nm CMOS, which are still the most widely adopted in sensing applications. In fact, because of the limited number of available metal levels, the capacitances are implemented close to the substrate being more subject to oxide gradients due to the surrounding active circuits [11,12]. In this work, a fully-differential 14-bit SAR ADC is proposed for moderatehigh resolution sensing applications in a 350-nm CMOS technology (see Fig.…”

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confidence: 99%

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A 70.7-dB SNDR 100-kS/s 14-b SAR ADC with attenuation capacitance calibration in 0.35-µm CMOS

Brenna

Bonfanti

Lacaita

2016

Analog Integr Circ Sig Process

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In sensor applications, low-power and moderate-high resolution analog-to-digital converters (ADCs) are needed to convert the analog front-end signal output. Such systems are often multi-channel and require analog multiplexing. In these cases, even when high resolutions are required, continuous time ΔΣ ADCs can’t be adopted, and an efficient data-conversion must be achieved relying on different topologies, typically successive approximation-register (SAR) ADCs. Since these systems are often implemented in CMOS processes like 250- and 350-nm CMOS to benefit from a large supply voltage, the SAR ADC design is challenging due to the technology mismatch and to the limited number of metals available to optimize the layout. This paper presents a SAR ADC implemented in 350-nm CMOS technology with a physical resolution of 14 bits using a binary weighted with attenuation capacitor array. The proposed converter exploits a semi-custom and isotropic unit capacitance with ground shield to avoid proximity effects and parasitic capacitances across its terminals, an optimized capacitive array layout insensitive to both linear and radial oxide gradients, and an efficient calibration algorithm to compensate the parasitic capacitances that worsen the converter linearity. At 1.8-V supply and 100-kSps sampling frequency, the proposed ADC achieves an SNDR of 70.7Â dB, an SFDR of 81.8Â dB, an ENoB of 11.45 and a power consumption of 43.4μW, corresponding to a figure-of-merit (FoM) of 155Â fJ/conv.step. To the best of our knowledge, this figure is the best among SAR converters implemented in 350-nm or less scaled technologies, and in-line with other ADCs featuring an SNDR larger than 70Â dB

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Section: Array Structurementioning

confidence: 99%

Section: Non-linearity In Capacitive Dacsmentioning

confidence: 99%

mentioning

confidence: 99%

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A 70.7-dB SNDR 100-kS/s 14-b SAR ADC with attenuation capacitance calibration in 0.35-µm CMOS

Brenna

Bonfanti

Lacaita

2016

Analog Integr Circ Sig Process

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“…After digital calibration, the codes remain unchanged or will be multiplied by 4 before the final output, when IRC is set to 1 and 0, respectively. Therefore, some improvements based on the designs in [105,106] have been made in the proposed high voltage bootstrapped switch (HVBS). the schematic of the proposed HVBS, which deploys only 1.2-V and 3.3-V transistors, operating at 1.2 V and achieving an input swing of 0~4.5 V. Fig.…”

Section: Input Rangementioning

confidence: 99%