A 50Mvertices/s graphics processor with fixed-point programmable vertex shader for mobile applications

Sohn, Ju-Ho; Woo, Jeong-Ho; Lee, Min-Wuk; Kim, Hye-Jung; Woo, Ramchan; Yoo, Hoi‐Jun

doi:10.1109/isscc.2005.1493934

Cited by 6 publications

(2 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In this research [6], we designed and tested a fixedpoint multimedia co-processor with programmable SIMD vertex shader for the ARM-10 based mobile graphics processor [7]. The ARM-10 co-processor architecture with dual operations is utilized for implementation and multimedia extensions.…”

Section: Introductionmentioning

confidence: 99%

Design and Test of Fixed-point Multimedia Co-processor for Mobile Applications

Sohn

Woo

Yoo

et al. 2006

Proceedings of the Design Automation &Amp;amp;amp; Test in Europe Conference

View full text Add to dashboard Cite

Abstract:In this research, a fixed-point multimedia co-processor is designed and tested into an ARM-10 based mobile graphics processor for portable 2-D and 3-D multimedia applications. The fixed-point co-processor architecture with dual operations realizes advanced 3-D graphics algorithms and various streaming multimedia functions in a single hardware while consuming low power. The instruction-wise clock gating on fixed-point SIMD datapath allows fine-grained power control in application-specific manner. The co-processor takes 10.2mm 2 in 0.18µm 6-metal standard CMOS logic process and achieves 50Mvertices/s graphics performance with 75.4mW power consumption. The implemented chip is successfully demonstrated on the development board equipped with software graphics library and evaluation environment.

show abstract

Section: Introductionmentioning

confidence: 99%

Design and Test of Fixed-point Multimedia Co-processor for Mobile Applications

Sohn

Woo

Yoo

et al. 2006

Proceedings of the Design Automation &Amp;amp;amp; Test in Europe Conference

View full text Add to dashboard Cite

show abstract

“…In this work, we designed and implemented a fixedpoint multimedia co-processor with programmable SIMD vertex shader for the ARM-10 based mobile graphics processor [6]. The fixed-point datapath is used to reduce the power consumption because only simple integer arithmetic circuits can be used in complex multimedia operations.…”

Section: Introductionmentioning

confidence: 99%

A fixed-point multimedia co-processor with 50mvertices/s programmable SIMD vertex shader for mobile applications

Sohn¹,

Woo²,

Woo³

et al.

Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.

View full text Add to dashboard Cite

A fixed-point multimedia co-processor is designed and integrated into an ARM-10 based mobile graphics processor for portable 2-D and 3-D multimedia applications. The user-programmable SIMD vertex shader with ARM-10 co-processor architecture realizes advanced 3-D graphics algorithms and various multimedia functions. Different from conventional ARM co-processor architecture, the multimedia co-processor implements dual operations, by which parallel and streaming multimedia processing is enabled in mobile applications. For low power consumption, fixed-point SIMD Datapath is designed with instruction-wise clock gating. The co-processor takes 10.2mm 2 in 0.18µm 6metal standard CMOS logic process and achieves 50Mvertices/s graphics performance with 75.4mW power consumption.

show abstract

A high performance floating-point special function unit using constrained piecewise quadratic approximation

Petra

Strollo

2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

A special function unit, able to compute square root, reciprocal square root, logarithm and exponential functions is presented in this paper. The system supports single precision IEEE-754 floating-point standard and uses a novel constrained piecewise quadratic interpolation technique to approximate the implemented functions. The proposed approach allows to reduce look-up table size of 40% with respect to previously proposed techniques. The SFU has been implemented in a test chip in 0.18 m CMOS. A maximum clock frequency of 420MHz and a power dissipation of 160mW@420MHz have been measured.

show abstract

A 50Mvertices/s graphics processor with fixed-point programmable vertex shader for mobile applications

Cited by 6 publications

References 4 publications

Design and Test of Fixed-point Multimedia Co-processor for Mobile Applications

Design and Test of Fixed-point Multimedia Co-processor for Mobile Applications

A fixed-point multimedia co-processor with 50mvertices/s programmable SIMD vertex shader for mobile applications

A high performance floating-point special function unit using constrained piecewise quadratic approximation

Contact Info

Product

Resources

About