A 500 MHz, 68% efficient, fully on-die digitally controlled buck Voltage Regulator on 22nm Tri-Gate CMOS

Krishnamurthy, Harish K.; Vaidya, Vaibhav; Kumar, Pankaj; Matthew, George E.; Weng, Sheldon; Thiruvengadam, Bharani; Proefrock, Wayne; Ravichandran, Krishnan; De, Vivek

doi:10.1109/vlsic.2014.6858438

Cited by 49 publications

(23 citation statements)

References 4 publications

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“…Hence, v ds,TN2 decreases and the gate-drain voltage of TN 2 increases until TN 2 enters the saturation region at t = t 2 . Subsequently, during t 2 < t < t 4 , negative drainsource voltage and negative drain current are present in TN 2 .…”

Section: Waveforms During Switching Transientsmentioning

confidence: 99%

“…The two-level Half-Bridge with Stacked Transistors (HBST) configuration of Fig. 1 (a), proposed in [2], has been employed successfully in many of Intel's IVRs using FinFet 22 nm technology [3], [4]. Most recently, Intel also proposed a fully integrated voltage regulator with power transistors, decoupling capacitors, and inductors in the same die [5] using the HBST of Fig.…”

Section: Introductionmentioning

confidence: 99%

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Analysis and comparative evaluation of stacked-transistor half-bridge topologies implemented with 14 nm bulk CMOS technology

Bezerra¹,

Aljameh²,

Krismer³

et al. 2017

2017 IEEE 18th Workshop on Control and Modeling for Power Electronics (COMPEL)

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Abstract-Integrated Voltage Regulators (IVRs) have become a viable solution for microprocessor's power delivery. The active parts of the most recent IVRs are built in deep-submicron CMOS technologies and use stacked transistors to allow for the use of advanced low voltage devices with superior switching performance compared to the higher voltage long-channel devices. This paper evaluates three different topologies of CMOS half-bridge converters with respect to efficiency, implementation effort, suitability for on-chip integration, and multiphase applications: the conventional half-bridge converter, the half-bridge converter with conventional Active Neutral Point Clamping (ANPC), and a halfbridge converter with a modified circuit to achieve ANPC. Indepth analysis of the transient processes during switching for all three converters, based on Cadence simulations, reveal that both half-bridge converters with ANPC achieve proper balancing of the blocking voltages of the main transistors and are capable to attain similar efficiencies of 93% at an output power of 200 mW, input and output voltages of 1.6 V and 0.8 V, respectively, and a switching frequency of 150 MHz, which is 1% higher than the one attained with the conventional half-bridge converter. Of the two ANPC half-bridge converters, however, the proposed topology allows to completely turn off its entire power stage or parts of it, features less efficiency sensitivity to variations of dead-time, and achieves the peak efficiency at relatively higher dead-time values. These qualities render the proposed topology particularly suitable for multiphase systems and low load operation.

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Section: Waveforms During Switching Transientsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Analysis and comparative evaluation of stacked-transistor half-bridge topologies implemented with 14 nm bulk CMOS technology

Bezerra¹,

Aljameh²,

Krismer³

et al. 2017

2017 IEEE 18th Workshop on Control and Modeling for Power Electronics (COMPEL)

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“…Equation (13) shows that some losses components are decreasing while some others are increasing. However, even with a negligible R C OU T , P gain is positive until ∆I L P H reaches √ 6 × I OU T , condition which is never satisfied in continuous conduction mode -at the limit, ∆I L P H is equal to 2 × I OU T .…”

Section: Two-phase Convertermentioning

confidence: 99%

A review of state-of-the-art and proposal for high frequency inductive step-down DC–DC converter in advanced CMOS

Neveu¹,

Allard²,

Martin³

2016

Analog Integr Circ Sig Process

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This paper reviews the state-of-the-art of high switching frequency, integrated DC-DC converters and presents the main trade-offs and challenges emerging from this review. Various converter structures (1phase buck, 2-phase buck, 2-phase coupled buck and 3level converter) are then discussed and analyzed through simulation from a losses point-of-view. Considering the review, the architecture analysis and the technology model, 4 converters are designed for a given set of specifications: 3.3 V to 1.2 V, 280 mA output current at high switching frequency (100-200 MHz) in 40 nm bulk CMOS. A cascode power stage is used in order to enhance power conversion efficiency, and 1-phase and 2phase structures are designed. Post-layout simulation results are presented, showing an efficiency above 90 % for a 2-phase converter. Keywords DC-DC conversion • High frequency • CMOS • State-of-the-art • Low voltage • Buck 1 Introduction Voltage conversion is a key enabler for large digital SoCs (Systems-on-Chip). There is a need to get the converter closer to its load in order to reduce resistive losses through PCB (Printed Circuit Board) traces, enable dynamic voltage scaling for more energy efficient This work is supported by the European Commission through the Seventh Framework Programme (FP7), under the project grant PowerSWIPE No. 318529.

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“…2 (b). Fully integrated IVRs realize very low parasitics of the supply lines and enable a reduction of the number of supply connections [6]; (b) fully ondie IVR [7]- [9]; (c) and (d) hybrid IVRs where the half-bridges are on the microprocessor die and the main passive components (inductors and capacitors) integrated into the package [10]- [12] or the silicon interposer [13]- [15].…”

Section: Introductionmentioning

confidence: 99%

“…between the package and the microprocessor die, due to the reduced total input current. However, these benefits come at the cost of substantial chip area being sacrificed for the IVRs' components [7], [8] and / or highly challenging realization of chip-integrated inductors, e.g., due to the need of complex Through Silicon Vias (TSVs) [9] and additional Back End Of Line (BEOL) post-processing steps [8]. In addition, the chip technology node used for the microprocessor defines stringent design constraints, which considerably limit the flexibility of the converter design.…”

Section: Introductionmentioning

confidence: 99%

Electrical and Thermal Characterization of an Inductor-Based ANPC-Type Buck Converter in 14 nm CMOS Technology for Microprocessor Applications

Bezerra

Krismer

Kolar

et al. 2020

IEEE Open J. Power Electron.

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Integrated Voltage Regulators (IVRs) are attractive substitutes for conventional voltage regulators located on the motherboards, due to outstanding dynamic performances and superior power densities. IVRs operate with switching frequencies in the range of 100 MHz and are assembled in highly compact packages close to the microprocessor load. This paper presents a comprehensive characterization of a PCB-and inductorbased four-phase ANPC-type IVR that uses a Power Management IC (PMIC) implemented in a 14 nm CMOS technology node. The characterization is based on the results of electrical measurements, thermal inspections of the chip surface, and simulations, which enables the separation of the total losses into on-chip and off-chip loss components and the allocation of important loss components inside the chip. The investigated IVR achieves a maximum efficiency of 84.1 % at an output power of Pout = 640 mW and a switching frequency of fs = 50 MHz. The thermal measurements reveal that the maximum efficiency of the PMIC itself is between 88 % and 90 % at fs = 50 MHz and Pout ∈ [500 mW, 600 mW]; at Pout = 890 mW, a chip current density of 24.7 A/mm 2 is achieved. The findings in particular point out that the losses in the chip-internal interconnections, i.e., the conductors of the Power Distribution Network (PDN) and the twelve stacked metal layers below the PDN, have a substantial contribution to the total losses. Furthermore, the combination of Cadence post-layout simulations with impedance networks obtained from an appropriate software tool, e.g., FastHenry, is found to establish a suitable toolbox for estimating losses in IVRs.

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A 500 MHz, 68% efficient, fully on-die digitally controlled buck Voltage Regulator on 22nm Tri-Gate CMOS

Cited by 49 publications

References 4 publications

Analysis and comparative evaluation of stacked-transistor half-bridge topologies implemented with 14 nm bulk CMOS technology

Analysis and comparative evaluation of stacked-transistor half-bridge topologies implemented with 14 nm bulk CMOS technology

A review of state-of-the-art and proposal for high frequency inductive step-down DC–DC converter in advanced CMOS

Electrical and Thermal Characterization of an Inductor-Based ANPC-Type Buck Converter in 14 nm CMOS Technology for Microprocessor Applications

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