A 50-GHz-small-signal-bandwidth 50 GSa/s Track&amp;amp;Hold Amplifier in InP DHBT technology

Deza, J.; Ouslimani, A.; Konczykowska, A.; Kasbari, Abed-Elhak; Riet, M.; Godin, J.; Pailler, G.

doi:10.1109/mwsym.2012.6259523

Cited by 10 publications

(5 citation statements)

References 5 publications

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“…Sampling rate and bandwidth of reported THAs have reached to 40 Gsampling/s and 19 GHz, respectively, for SiGe BiCMOS process, 30 Gsampling/s and 13 GHz, respectively, for CMOS process, 70 Gsampling/s and 51 GHz, respectively, for InP HBT process, 90 Gsampling/s and 19.9 GHz, respectively, for SOI CMOS process during the past 10 years.…”

Section: Introductionmentioning

confidence: 99%

A low sampling clock, high bandwidth, master‐slave track and hold amplifier

Zhang

Zhou

Liu

et al. 2019

Int J RF Microw Comput Aided Eng

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A fully-differential master-slave track and hold amplifier (MSTHA), with one-input, four-output and nearly 20 GHz bandwidth is designed and fabricated in 0.13-μm SiGe BiCMOS technology. Operating with a single +3.3 V supply, 0 V input directvoltage, 2 GHz sampling clock input and 5 dBm input power, the MSTHA achieves a spurious free dynamic range (SFDR) of less than −31 dB up to 20 GHz, 0.5 mV rms output noise amplitude (RMS, root of mean square) and totally power consumingbandwidth, master-slave, MSTHA, SFDR, SiGe BiCMOS

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Section: Introductionmentioning

confidence: 99%

A low sampling clock, high bandwidth, master‐slave track and hold amplifier

Zhang

Zhou

Liu

et al. 2019

Int J RF Microw Comput Aided Eng

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“…In 2011, a SiGe-based THA had much lower DC power consumption with a total harmonic distortion (THD) of up to −50 dBc [20]. THAs designed in articles published in 2012 [21]- [24] have an input track-mode bandwidth wider than 40 GHz, which is two to three times wider than that of previously reported THAs. In 2013, an advanced 28-nm CMOS process was used to mitigate low-pass response results caused by the parasitic capacitance of devices [25], and in 2014, THAs were widely investigated by using a time-interleaved architecture to enhance the sampling rate [26]- [28].…”

Section: Introductionmentioning

confidence: 99%

“…In 2015, 2016, and 2017, several different THA topologies were summarized and widely employed to simultaneously achieve high speed, high linearity, high resolution, and low DC power consumption [29]- [35]. Although operating speeds of up to 40-GS/s sampling rate [19] and 40-GHz bandwidth [21] are attainable, the cost of the circuits is much higher because of the more advanced process used. Moreover, the operating speed of samplers is still restricted by the unity current gain frequency (f T ) of the device.…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of 0.5-<inline-formula> <tex-math notation="LaTeX">$f_{\mathrm{T}}$ </tex-math> </inline-formula> Bandwidth THAs With Resolution Enhancement Techniques in 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu$ </tex-math> </inline-formula>m SiGe Process

et al. 2019

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This paper presents the design and analysis of microwave and millimeter-wave (MMW) high-linear track-and-hold amplifiers (THAs) for high-speed data conversion systems. The silicon germanium (SiGe) process utilized in the proposed circuits is analyzed in detail and its several merits are demonstrated, including operating speed, linearity, and resolution. Bandwidth extension techniques, such as peaking, Darlington, and distributed topologies, are adopted to further enhance the operating speed of the proposed THAs up to a 0.5-unity current gain frequency (f T) of the transistor. The switched emitter-follower (SEF) as well as the switched capacitor (SC) track-and-hold (T/H) stages are modified using pedestal error reduction techniques, including a cascode stage and differential cancellation, to further enhance the overall resolution of the THAs. The proposed cascoded SEF-based T/H circuit with a modified Darlington-based input buffer has a track-mode bandwidth of up to 0.5-f T , a maximum spurious-free dynamic range (SFDR) of 45.1 dBc, and dc power consumption of 94.3 mW. Moreover, the proposed differential cancellation SCbased T/H circuit with an input buffer based on the distributed bandwidth extension technique exhibits an operating speed of up to 0.32-f T , an SFDR of 47.9 dBc, and dc power consumption of 180.1 mW. Both proposed THAs are suitable for low-power, high-speed MMW conversion systems without incurring a high cost. Moreover, by using the proposed design methodology, a sampling rate up to tens of gigahertz can be easily achieved with time-interleaved architecture. INDEX TERMS CMOS/SiGe RFIC, microwave integrated circuits (ICs), mixed signal design, high-speed analog IC design, sampling circuits.

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“…Track&Hold Amplifier (THA) which is the main ADC block and whose function is to hold and to store an analog signal value during the hold mode operation, requires a wide bandwidth a good isolation and a sufficient resolution. 50 GSa/s THA [1,2] realized in SiGe and InP technologies using the Switched Emitter Follower (SEF) structure has been reported.…”

Section: Introductionmentioning

confidence: 99%

A 60 GSa/s InP-DHBT-THA with 50 GHz Bandwidth for High Bit Rate Communication Systems

Deza

Ouslimani

Konczykowska

et al. 2013

Proceedings of the 2nd International Symposium on Computer, Communication, Control and Automation

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-A 60 GSa/s THA is designed and realized in InP-DHBT process. The THA presents a small signal bandwidth of 50 GHz. For +4 dBm and -4 dBm input powers, 60 GSa/s spectral measurements give a THD of -37.3 dB and -51.3 dB for input frequency up to 2 GHz and a THD of -30.1 dB and -38.7 dB up to 15 GHz. Temporal measurement illustrates the THA operation for a 2 GHz sinusoid input signal sampled at 60 GHz.

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A 50-GHz-small-signal-bandwidth 50 GSa/s Track&Hold Amplifier in InP DHBT technology

Cited by 10 publications

References 5 publications

A low sampling clock, high bandwidth, master‐slave track and hold amplifier

A low sampling clock, high bandwidth, master‐slave track and hold amplifier

Design and Analysis of 0.5-<inline-formula> <tex-math notation="LaTeX">$f_{\mathrm{T}}$ </tex-math> </inline-formula> Bandwidth THAs With Resolution Enhancement Techniques in 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu$ </tex-math> </inline-formula>m SiGe Process

A 60 GSa/s InP-DHBT-THA with 50 GHz Bandwidth for High Bit Rate Communication Systems

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