A 5 V, 118 dB ΣΔ analog-to digital converter for wideband digital audio

Leung, Ka; Swanson, Eric J.; Zhu, Sarah

doi:10.1109/isscc.1997.585340

Cited by 8 publications

(6 citation statements)

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“…The audio ADC in [128] actually dates from 1997 and still has a distinct spot in SNDR versus f nyq comparison. In Fig.…”

Section: ) Techniques For Narrowband Adcsmentioning

confidence: 99%

Design Techniques for Energy-Efficient Analog-to-Digital Converters

Jang,

Tang,

Lim

et al. 2023

IEEE Open J. Solid-State Circuits Soc.

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The energy efficiency of analog-to-digital converters (ADCs) has improved steadily over the past 40 years, with the best reported ADC efficiency improving by nearly six orders of magnitude over the same period. The best figure-of-merit (FoM) is achieved with a limited class of ADC in terms of resolution and speed, but the coverage of the best FoM ADC has been expended. Many ADCs with the record FoM open up new applications and often incorporate multiple combinations of architectural and circuit innovations. It would be very interesting to follow a path of relentless optimization that could be useful to further expand the operating bandwidth of energy-efficient ADCs. To help along this path, this review article discusses the design techniques that focus on optimizing energy efficiency, involving successive approximation, pipelining, noise-shaping, and continuous-time operation.INDEX TERMS Analog-to-digital converter (ADC), continuous-time (CT), delta-sigma modulation, energy efficient, low power, noise-shaping (NS), pipelining, successive approximation.

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“…The audio ADC in [128] actually dates from 1997 and still has a distinct spot in SNDR versus f nyq comparison. In Fig.…”

Section: ) Techniques For Narrowband Adcsmentioning

confidence: 99%

Design Techniques for Energy-Efficient Analog-to-Digital Converters

Jang,

Tang,

Lim

et al. 2023

IEEE Open J. Solid-State Circuits Soc.

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“…1 [1]. Indeed, these highresolution general-purpose data converters [2]- [10] are not usually setting the absolute state-of-art value of the Schreier figure of merit FOMS . = SNDRmax+10 log fnyq 2P d [dB], where SNDRmax, fnyq and P d stand for the ADC peak SNDR, equivalent Nyquist sampling frequency and power consumption, respectively.…”

Section: Introductionmentioning

confidence: 99%

“…In the above design scenario, several ∆ΣM architectural strategies are employed in order to improve dynamic range: high-order (≥ 4) single-loop noise shaping [2], [3], [6], [7], which is prone to instability; multi-stage noise shaping (MASH) [4], [8] that tends to suffer from technology mismatching at the reconstruction filtering; and SAR-driven Zoom ∆ΣMs [9], [10], whose internal full-scale control introduces glitches and excess of out-of-band harmonics. At CMOS circuit level, flicker noise contributions in the kHz range are commonly attenuated in fully differential topologies by the use of chopping [3], [4], [10] despite the resulting ripple and harmonics.…”

Section: Introductionmentioning

confidence: 99%

A 0.8mW 50kHz 94.6dB-SNDR Bootstrapping-Free SC Delta-Sigma Modulator ADC with Flicker Noise Cancellation

Suanes

Terés

Dei

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper presents a 0.8-mW 0.2-mm 2 9-level second-order single-loop SC Delta-Sigma modulator (ΔΣM) ADC in 1.8-V 0.18-μm CMOS technology for low-power high-resolution sensing applications. The ΔΣM circuit features 94.6-dB peak SNDR in 50-kHz bandwidth and 103.5 dB SFDR up to -1 dB FS input for 2-Vpp differential full scale. The proposed built-in CDS flicker noise cancellation allows a net improvement of 10 dB FOM S . The bootstrapping-free CMOS circuits incorporate variable-mirror Class-AB switched OpAmps and a 10-μW resistor-less flash quantizer. The obtained 172.6-dB FOM S is competitive within the state-of-art high-resolution (SNDR > 90 dB) and generalpurpose (bandwidth > 20 kHz) SC ΔΣM ADCs.

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“…Therefore, it can be modeled as a gain of one and an additive noise source E(z) that symbolizes the unavoidable inherent quantization noise. In order to make the input signal to be tracked more accurately while maintaining linearity, it is suggested to use a three-level quantizer instead of one-bit one in each stage of the proposed delta-sigma modulator [49]. Now, just like one-bit quantizer, the output of three-level quantizer have the fixed three analog output levels whose middle-level output is the average of two extreme outputs and therefore it is also inherently linear.…”

Section: The Proposed 2-2-2 Cascade Architecturementioning

confidence: 99%

Design of multi-standard and wideband delta-sigma modulator

Du¹

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support to my research. It is a great opportunity to study and work with their supervision. In addition, I would like to thank the members of my thesis examination committee for their time and feedback to improve the quality of my thesis.I also want to thank the members of my laboratory mates for their helping on technical problems for my project. Thanks to my friends in Center of Integrated Circuits and Systems (CICS). I appreciate the friendships and support from them. Thanks to CICS for workstation of CADENCE and Nan YangTechnological University for funding this project.Finally, I am very grateful to my family for their encouragement, understanding and moral support, which made this work into a completed endeavor. Especially, I would like to express my deep appreciation to my husband, Wang KaiFei who has accompanied me with his strong encouragement and support in these years. I also thank my daughter YaXin for the joy she has added to my life.

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A 5 V, 118 dB ΣΔ analog-to digital converter for wideband digital audio

Cited by 8 publications

References 1 publication

Design Techniques for Energy-Efficient Analog-to-Digital Converters

Design Techniques for Energy-Efficient Analog-to-Digital Converters

A 0.8mW 50kHz 94.6dB-SNDR Bootstrapping-Free SC Delta-Sigma Modulator ADC with Flicker Noise Cancellation

Design of multi-standard and wideband delta-sigma modulator

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