A 5.5GS/s 28mW 5-bit flash ADC with resonant clock distribution

Ma, Wei-Hsiang; Kao, Jerry C.; Papaefthymiou, Marios C.

doi:10.1109/esscirc.2011.6044888

Cited by 6 publications

(2 citation statements)

References 9 publications

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“…There are different logic styles to implement the design of the thermometer code to Gray and Gray to binary code encoders. To avoid the static power dissipation and to achieve high speed, the implementation of encoder is validated using DCVSL [26]. DCVSL gate has speed advantage over pseudo-NMOS logic, there by the parasitic capacitance of the output node of DCVSL logic gets reduced and faster response is achieved.…”

Section: Implementation Of the Proposedmentioning

confidence: 99%

Implementation of Power Efficient Flash Analogue-to-Digital Converter

Lakshmi

Srinivasulu

Pittala

2014

Active and Passive Electronic Components

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An efficient low power high speed 5-bit 5-GS/s flash analogue-to-digital converter (ADC) is proposed in this paper. The designing of a thermometer code to binary code is one of the exacting issues of low power flash ADC. The embodiment consists of two main blocks, a comparator and a digital encoder. To reduce the metastability and the effect of bubble errors, the thermometer code is converted into the gray code and there after translated to binary code through encoder. The proposed encoder is thus implemented by using differential cascade voltage switch logic (DCVSL) to maintain high speed and low power dissipation. The proposed 5-bit flash ADC is designed using Cadence 180 nm CMOS technology with a supply rail voltage typically ±0.85 V. The simulation results include a total power dissipation of 46.69 mW, integral nonlinearity (INL) value of −0.30 LSB and differential nonlinearity (DNL) value of −0.24 LSB, of the flash ADC.

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Section: Implementation Of the Proposedmentioning

confidence: 99%

Implementation of Power Efficient Flash Analogue-to-Digital Converter

Lakshmi

Srinivasulu

Pittala

2014

Active and Passive Electronic Components

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“…The 5.5GS/s ADC in [13] shows a slightly better FoM but has ERBW lower than the Nyquist frequency and lower resolution. The better power efficiency of [13] is achieved by using an inductor for resonant clock distribution at the expense of silicon area and low flexibility to change the conversion rate.…”

Section: Experimentamentioning

confidence: 99%

A 6-bit 6-GS/s 95mW background calibrated flash ADC with integrating preamplifiers and half-rate comparators in 32nm LP CMOS

Radice

Bruccoleri

Ganzerli

et al. 2013

2013 Proceedings of the ESSCIRC (ESSCIRC)

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A 6-bits 6-GS/s flash ADC is presented. Singlestage integrators are proposed as preamplifiers to drive the comparators. Compared to single-stage voltage amplifiers, integrators limit the gain-bandwidth requirements leading to lower power dissipation and smaller device size. Comparators are interleaved and clocked at half rate, limiting dissipation thanks to the longer available regeneration time. Offsets of the front-end are continuously calibrated in background. The ADC, realized in a 32nm Low Power CMOS technology proves a very robust operation with SNDR degradation of only 1.5dB going from 1GS/s to 6GS/s. ENOB at 6GS/s with Nyquist frequency input is 5.25 with power dissipation of 95mW from 1V supply. The corresponding FoM is 416fJ/conv. To the Authors knowledge the converter displays also the highest speed among CMOS flash ADCs with more than 4 effective bits of resolution.

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A quantitative design methodology for high-speed interpolation/averaging ADCs

Tang

Peng

et al. 2017

Integration

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A 5.5GS/s 28mW 5-bit flash ADC with resonant clock distribution

Cited by 6 publications

References 9 publications

Implementation of Power Efficient Flash Analogue-to-Digital Converter

Implementation of Power Efficient Flash Analogue-to-Digital Converter

A 6-bit 6-GS/s 95mW background calibrated flash ADC with integrating preamplifiers and half-rate comparators in 32nm LP CMOS

A quantitative design methodology for high-speed interpolation/averaging ADCs

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