A 5.3GHz 8T-SRAM with Operation Down to 0.41V in 65nm CMOS

Chang, Leland; Nakamura, Yohei; Montoye, Robert K.; Sawada, Jun; Martin, Andrew K.; Kinoshita, K.; Gebara, F.H.; Agarwal, Kanak; Acharyya, Dhruva; Haensch, Wilfried; Hosokawa, Kohji; Jamsek, Damir A.

doi:10.1109/vlsic.2007.4342739

Cited by 101 publications

(52 citation statements)

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“…Therefore, cell designs with PUWG should be floor-planned with spatially adjacent words, where word-size may restrict the row length. Moreover, since bits from different words are no longer spatially interleaved, additional area penalty may result from the interleaving of ECC codes [45].…”

Section: Architectural Considerationsmentioning

confidence: 99%

SRAM Read/Write Margin Enhancements Using FinFETs

Carlson

Guo

Balasubramanian

et al. 2010

IEEE Trans. VLSI Syst.

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Abstract-Process-induced variations and sub-threshold leakage in bulk-Si technology limit the scaling of SRAM into sub-32 nm nodes. New device architectures are being considered to improve control and reduce short channel effects. Among the likely candidates, FinFETs are the most attractive option because of their good scalability and possibilities for further SRAM performance and yield enhancement through independent gating. The enhancements to read/write margins and yield are investigated in detail for two cell designs employing independently gated FinFETs. It is shown that FinFET-based 6-T SRAM cells designed with pass-gate feedback (PGFB) achieve significant improvements in the cell read stability without area penalty. The write-ability of the cell can be improved through the use of pull-up write gating (PUWG) with a separate write word line (WWL). The benefits of these two approaches are complementary and additive, allowing for simultaneous read and write yield enhancements when the PGFB and PUWG designs are used in combination.

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Section: Architectural Considerationsmentioning

confidence: 99%

SRAM Read/Write Margin Enhancements Using FinFETs

Carlson

Guo

Balasubramanian

et al. 2010

IEEE Trans. VLSI Syst.

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“…However, by leveraging the asymmetric nature of HETTs, this unwanted reverse-direction charging current is eliminated without the cost of an additional transistor, as in the well-known 8T structures [21]. The HETT 7T SRAM is estimated to have <15% area overhead over a standard 6T while 8T SRAM exhibits 29% cell area overhead [22]. Figure 16 shows that two read transistors (NRD in Figure 14) from adjacent cells can be abutted in 7T SRAM, making the overhead for two 7T cells equal to that of one 8T cell.…”

Section: T Sram For Hettmentioning

confidence: 99%

Low power circuit design based on heterojunction tunneling transistors (HETTs)

Kim

Lee

Cai

et al. 2009

Proceedings of the 2009 ACM/IEEE International Symposium on Low Power Electronics and Design

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The theoretical lower limit of subthreshold swing in MOSFETs (60 mV/decade) significantly restricts low voltage operation since it results in a low ON to OFF current ratio at low supply voltages. This paper investigates extremely-low power circuits based on new Si/SiGe HEterojunction Tunneling Transistors (HETTs) that have subthreshold swing < 60 mV/decade. Device characteristics as determined through Technology Computer Aided Design (TCAD) tools are used to develop a Verilog-A device model to simulate and evaluate a range of HETT-based circuits. We show that a HETT-based ring oscillator (RO) shows a 9−19X reduction in dynamic power compared to a CMOS RO. We also explore two key differences between HETTs and traditional MOSFETs, namely asymmetric current flow and increased Miller capacitance, analyzing their effect on circuit behavior and proposing methods to address them. Finally, HETT characteristics have the most dramatic impact on SRAM operation and hence we propose a novel 7-transistor HETT-based SRAM cell topology to overcome, and take advantage of, the asymmetric current flow. This new HETT SRAM design achieves 7−37X reduction in leakage power compared to CMOS.

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“…1 shows a simplified SRAM array with highlighted critical parameters relevant to the energy analysis. An 8T decoupled SRAM cell [25] is employed due to its popularity in ultra-low voltage SRAM design. The effect of an optimal device selection on the energy of SRAM peripheral circuits is insignificant compared to that on SRAM arrays.…”

Section: Sram Energy Modelingmentioning

confidence: 99%