Low power circuit design based on heterojunction tunneling transistors (HETTs)

Kim, Dae-Yeon; Lee, Yoonmyung; Cai, Jin; Lauer, Isaac; Chang, Leland; Koester, Steven J.; Sylvester, Dennis; Blaauw, David

doi:10.1145/1594233.1594287

Cited by 65 publications

(35 citation statements)

References 15 publications

(15 reference statements)

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“…To perform circuit simulations, we capture the I d -V g transfer characteristics of the CMOS and the HTFET obtained using the models discussed in section II-A, in a Verilog-A lookup table [14], [15], [16]. Because of delayed onset of saturation in the HTFET, the Voltage Transfer Characteristics (VTC) of a HTFET inverter are considerably degraded compared to that of a CMOS inverter, as shown in Fig.…”

Section: A Tfet and Cmos Device Modelsmentioning

confidence: 99%

“…Further, due to uni-directional conduction, the Write-SNM for the TFET SRAM cell shown in Fig. 7(A) is zero [14].…”

Section: A Tfet and Cmos Device Modelsmentioning

confidence: 99%

“…It has been shown that a 6T TFET SRAM with either inward or outward-facing access transistors, cannot simultaneously do both read and write [14]. In order to circumvent this limitation, a 6T TFET SRAM with one-inward and one-outward facing access transistor has been proposed [15].…”

Section: Design Of 8t and 10t Tfet Srammentioning

confidence: 99%

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Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design

Saripalli

Datta

Narayanan

et al. 2011

2011 IEEE/ACM International Symposium on Nanoscale Architectures

119

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Abstract-Steep sub-threshold Interband Tunnel FETs (TFETs) are promising candidates for low supply voltage applications with higher switching performance than traditional CMOS. Unlike CMOS, TFETs exhibit uni-directional conduction due to their asymmetric source-drain architecture, and delayed output saturation characteristics. These unconventional characteristics of TFETs pose a challenge for providing good read/write noise margin characteristics in TFET SRAMs. We provide an analysis of 8T and 10T TFET SRAM cells, including Schmitt-Trigger (ST) based cells, to address these shortcomings. By benchmarking a variety of TFET-based SRAM cells, we show the utility of the Schmitt-Trigger feedback mechanism in improving the read/write noise margins, thus enabling ultra low-VCC operation for TFET SRAMs. We also propose a variation model for studying the impact of device-level variation on TFET SRAM cells. We show that the TFET ST SRAM cell has sufficient variation tolerance to operate at low-VCC, and is a very promising cell to achieve a VCC-min of 124mV. The TFET ST cell operating at its VCC-min provides a 1.2x reduction in dynamic energy and 13x reduction in leakage power compared to the best CMOS-based SRAM implementation operating at it's VCC-min, while giving better performance at the same time.

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Section: A Tfet and Cmos Device Modelsmentioning

confidence: 99%

“…Further, due to uni-directional conduction, the Write-SNM for the TFET SRAM cell shown in Fig. 7(A) is zero [14].…”

Section: A Tfet and Cmos Device Modelsmentioning

confidence: 99%

See 1 more Smart Citation

Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design

Saripalli

Datta

Narayanan

et al. 2011

2011 IEEE/ACM International Symposium on Nanoscale Architectures

119

View full text Add to dashboard Cite

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“…Recently, many different TFET SRAMs have been explored to overcome this limitation [14][15][16][17]. By comparing those designs on several aspects (e.g.…”

Section: 2tunneling Field Effect Transistors (Tfets)mentioning

confidence: 99%

Hybrid CMOS-TFET based register files for energy-efficient GPGPUs

Tan

2013

International Symposium on Quality Electronic Design (ISQED)

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State-of-the-art General-Purpose computing on Graphics Processing Unit (GPGPU) is facing severe power challenge due to the increasing number of cores placed on a chip with decreasing feature size. In order to hide the long latency operations, GPGPU employs the fine-grained multithreading among numerous active threads, leading to the sizeable register files with massive power consumption. Exploring the optimal power savings in register files becomes the critical and first step towards the energyefficient GPGPUs. The conventional method to reduce dynamic power consumption is the supply voltage scaling, and the inter-bank tunneling FETs (TFETs) are the promising candidates compared to CMOS for low voltage operations regarding to both leakage and performance. However, always executing at the low voltage (so that low frequency) will result in significant performance degradation. In this study, we propose the hybrid CMOS-TFET based register files. To optimize the register power consumption, we allocate TFET-based registers to threads whose execution progress can be delayed to some degree to avoid the memory contentions with other threads, and the CMOS-based registers are still used for threads requiring normal execution speed. Our experimental results show that the proposed technique achieves 30% energy (including both dynamic and leakage) reduction in register files with little performance degradation compared to the baseline case equipped with naive power optimization technique.

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“…Using lower power supply voltage is one of the major solutions for decreasing device power consumption. Nowadays, circuits are designed to operate within the domains near the threshold-voltage as a result of these efforts to reduce supply voltage (V th ) [1] [2].…”

Section: Introductionmentioning

confidence: 99%

Design of Low Voltage and High-Speed BiCMOS Buffer for Driving Large Load Capacitor

Kaviani¹,

Sharifi

Dolatshahi³

et al. 2016

IJEM

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BICMOS circuits are interesting for designers when a high speed output driver is required especially in I/O circuits. Buffer is an important block in high speed circuits, so designing a buffer with high drive capability has a great effect on circuits with large load capacitor. This paper presents a new BiCMOS buffer which uses 32nm technology node for CMOS transistors and 0.18um technology node for BJT transistors. The proposed buffer operates properly in voltage ranges from 0.8v to 1.5v. The capacitor range is from 0.5pf to 200pf; the overshoot of the output in this capacitor range is less than 10% of the supply voltage that is negligible. The proposed design has improvements in delay for about %88 respectively compared to similar CMOS buffers with high capacitor values.

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Low power circuit design based on heterojunction tunneling transistors (HETTs)

Cited by 65 publications

References 15 publications

Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design

Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design

Hybrid CMOS-TFET based register files for energy-efficient GPGPUs

Design of Low Voltage and High-Speed BiCMOS Buffer for Driving Large Load Capacitor

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