A 5–13.5 Gb/s Multistandard Receiver With High Jitter Tolerance Digital CDR in 40-nm CMOS Process

Shu, Zhou; Huang, Shalin; Li, Zhipeng; Yin, Peng; Zang, Jiandong; Fu, Dongbing; Tang, Fang; Bermak, Amine

doi:10.1109/tcsi.2020.2991253

Cited by 9 publications

(3 citation statements)

References 35 publications

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“…The first term in (8) is the expression of the standard normal distribution, so (9) According to the Taylor expansion formula, we can know that exp(-y 2 /2)≈1-y 2 /2, so the second term in (8) can be obtained as: (10) Substituting ( 9) and ( 10) into (8), we can get (11) Similarly, we can have (12) Substituting ( 11) and ( 12) into (6), we can get In the simulation, we use pseudo random bit sequence (PRBS) code to simulate the real data streams, and the transformation probability of the data is equal. In other words, the transition density KTD of MMPD is 0.5, which is the same as BBPD.…”

Section: Linearization Of Mmpdmentioning

confidence: 99%

Analysis of Mueller-Muller Clock and Data Recovery Circuits with a Linearized Model

Feng

Chi

et al. 2022

Preprint

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With the development of high-speed analog-to-digital converter (ADC) based wireline receivers, Mueller-Muller clock and data recovery (MM-CDR) circuit also get more and more attention. But in the design stage, the MM-CDR circuit used in ADC-based wireline receiver is difficult to evaluate its loop performance, owing to the lack of linearized model of Mueller-Muller phase detector (MMPD). In this paper, by analyzing the slope and distribution of the signal at different positions, a linearized model of MMPD is proposed and the model is combined with an entire MM-CDR system to analyze the performance of the MM-CDR loop. Through the analysis of the linearized model and the verification of the actual simulation, we can know that when the VREF level in the MMPD is set equal to the amplitude of the main-cursor h0, the MMPD can obtain the maximum gain, and the jitter transfer function and jitter tolerance can achieve optimum performance.

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Section: Linearization Of Mmpdmentioning

confidence: 99%

Analysis of Mueller-Muller Clock and Data Recovery Circuits with a Linearized Model

Feng

Chi

et al. 2022

Preprint

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“…Both the MMPD and BBPD are nonlinear phase detectors, but since the judgment of the MMPD is affected by signal amplitude and the set value of Vref, its linearization is more complicated. The BBPD is not affected by signal amplitude, so its linearization model can be easily obtained by analyzing the relationships between its judgment responses and the size of the signal jitter, which was convenient for us to analyze the performance of our CDR circuit [22][23][24]. For a 50% transition density, the BBPD gain can be expressed as:…”

Section: The Working Principles Of Bbpdmentioning

confidence: 99%

A Digital Bang-Bang Clock and Data Recovery Circuit Combined with ADC-Based Wireline Receiver

Feng

Chi

et al. 2022

Electronics

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With the great increases in data transmission rate requirements, analog-to-digital converter (ADC)-based wireline receivers have received more and more attention due to their flexible and powerful equalization capabilities. Considering power consumption, baud-rate Mueller–Muller clock and data recovery (MM-CDR) circuits are widely used in ADC-based wireline receivers since MM-CDR circuits only need one sample signal per unit interval (UI). However, MM-CDR circuits need to set an additional Vref voltage to match the size of the main tap of the channel. If the Vref matching is not appropriate or the signal quality is good as a square wave, MM-CDR circuits cannot accurately lock on to a certain phase and instead drift within a phase range. Therefore, MM-CDR circuits are not as robust and stable as oversampled CDR circuits. In this study, a digital bang-bang clock and data recovery (DBB-CDR) circuit combined with an ADC-based wireline receiver was proposed. The DBB-CDR circuit could eliminate various unstable factors of MM-CDR circuits and achieve fast and robust phase locking without excessively increasing power consumption. A model of the DBB-CDR circuit was combined with an actual 32 Gb/s ADC-based wireline receiver, which was implemented in 28 nm CMOS technology to analyze the performance of the DBB-CDR circuit. The simulation results showed that the DBB-CDR circuit could achieve 0.42 UIpp JTOL@10MHz, and that the minimum JTOL value was 0.362 UIpp under a 0.04 UI variance of Gaussian jitter. The area and power consumption of the DBB-CDR circuit were only 64 μm2 and 0.02 mW, respectively; and the DBB-CDR circuit could also obtain very stable phase locking and demonstrated a fast frequency offset tracking ability when there was a frequency offset.

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“…Besides, both two equalization branches and the adjustable filter for the power detector enhance the adaptability while maintaining higher precision and adjustment speed. For SDDCDR, the firstorder PI-CDR is adopted to reduce the design difficulty, which improves the frequency offset tracking range and the tracking ability to SSC by increasing the operating frequency of DLF under the process constraints [27].…”

Section: Introductionmentioning

confidence: 99%

A 0.8-6Gb/s wireline receiver based on the spectrum-balancing equalizer and semi-digital dual loop CDR

Chen

Cai

Zhong

et al. 2023

IEICE Electron. Express

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In this work, a high-speed four-channel 0.8-6Gb/s wireline receiver was reported. Based on spectrum-balancing (SB) equalizer and slicer amplitude attenuator, it can be automatically adjusted to the most suitable state, avoiding the underbalanced or over-balance caused by amplitude mismatch. Moreover, a first-order semi-digital dual-loop clock and data recovery circuit (SDDCDR) with a high-speed digital loop filter (DLF) is also integrated to simplify the structure and improve the tracking ability of frequency offset. The prototype was fabricated on a 130nm CMOS process with a core area of 0.38 mm 2 for a single lane, consuming 97.3mW power at a 1.2V supply and tracking a 6966ppm frequency offset. In a 3m-cable test environment, the receiver sinusoidal jitter tolerance at high frequency is better than 0.22UI when 6Gb/s.

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A 5–13.5 Gb/s Multistandard Receiver With High Jitter Tolerance Digital CDR in 40-nm CMOS Process

Cited by 9 publications

References 35 publications

Analysis of Mueller-Muller Clock and Data Recovery Circuits with a Linearized Model

Analysis of Mueller-Muller Clock and Data Recovery Circuits with a Linearized Model

A Digital Bang-Bang Clock and Data Recovery Circuit Combined with ADC-Based Wireline Receiver

A 0.8-6Gb/s wireline receiver based on the spectrum-balancing equalizer and semi-digital dual loop CDR

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