A 4GSample/s 8b ADC in 0.35μm CMOS

Poulton, K.; Neff, Raymond K.; Muto, A.; Liu, Wei; Burstein, A.; Heshami, M.

doi:10.1109/isscc.2002.992176

Cited by 19 publications

(13 citation statements)

References 2 publications

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“…However, in the front-end S/H, where the clock is used to sample a continuous time signal, any deviation of the sampling moment from its ideal value results in an error voltage in the sampled signal equal to the signal change between these two moments. The clock skew between the sampling clocks of distributed S/H circuits can be calibrated by measuring its value and controlling tunable delays of a DLL [17]. Nevertheless, in general, calibration of the skew between S/H circuits has two significant drawbacks.…”

Section: A Time-interleaved Sample-and-holdmentioning

confidence: 99%

A 1.2V 55mW 12bits self-calibrated dual-residue analog to digital converter in 90 nm CMOS

Zjajo¹,

Gyvez²

2011

IEEE/ACM International Symposium on Low Power Electronics and Design

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Section: A Time-interleaved Sample-and-holdmentioning

confidence: 99%

A 1.2V 55mW 12bits self-calibrated dual-residue analog to digital converter in 90 nm CMOS

Zjajo¹,

Gyvez²

2011

IEEE/ACM International Symposium on Low Power Electronics and Design

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“…It is a basic building block suitable for several applications, e.g. fractional-N phase-locked loops (PLL) [1]- [4], (sub-)sampling oscilloscopes [5] [6], automatic test equipment (ATE) [7], direct digital frequency synthesis (DDFS) [8], polar transmitter [9], radar [10], phased-array system [11], and time-interleaved ADC timing calibrations [12]. This paper aims at improving the time resolution and linearity of a DTC.…”

Section: Introductionmentioning

confidence: 99%

A High-Linearity Digital-to-Time Converter Technique: Constant-Slope Charging

Palattella

Geraedts

et al. 2015

IEEE J. Solid-State Circuits

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“…Current-mode circuits have been avoided in high-speed and high-precision ADCs and a few published papers have advocated such designs [2], [3].…”

Section: Introductionmentioning

confidence: 99%

“…In [3], A 4 GS/s ADC with 7-bit ENOB was realized by using 32, 125 MS/s, current-mode 8-bit ADCs in parallel. The performance of current-mode 8-bit ADCs was satisfactory; however, it was obtained using a 3.3 V supply voltage.…”

Section: Introductionmentioning

confidence: 99%

A Current-mode ADC with Current Exchanging and Averaging Capabilities by Switching the Currents and Calculating Data in the Digital Domain

Yoshii

Mizutani

Sugimoto

2007

2007 IEEE Custom Integrated Circuits Conference

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A 2 V, 25 MS/s, current-mode and pipelined analog-todigital converter (ADC) which realizes a 1.5-bit bit-block architecture and uses a front-end current-mode sample-and-hold (S/H) circuit is described. In order to obtain the precise output current without suffering from poor current mismatch in a bitblock, the input and output currents in a current-mirror circuit are exchanged at every clock period. This produces signal currents at the output of a bit-block with positive and negative mismatch errors in turn. Since the analog-to-digital (A-D) converted digital codes of a bit-block contain these positive and negative mismatch errors, the errors are canceled out by taking the average of the consecutive digital codes at the output part of the ADC. A current-mode ADC using this proposed scheme has been fabricated by using 0.25 um CMOS devices. The results show that the effective number of bits (ENOB) is 7.6, that the spurious-free dynamic range (SFDR) is 48 dB, with a 20 MHz clock from a 2 V supply voltage.

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A 4GSample/s 8b ADC in 0.35μm CMOS

Cited by 19 publications

References 2 publications

A 1.2V 55mW 12bits self-calibrated dual-residue analog to digital converter in 90 nm CMOS

A 1.2V 55mW 12bits self-calibrated dual-residue analog to digital converter in 90 nm CMOS

A High-Linearity Digital-to-Time Converter Technique: Constant-Slope Charging

A Current-mode ADC with Current Exchanging and Averaging Capabilities by Switching the Currents and Calculating Data in the Digital Domain

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