A 1.2V 55mW 12bits self-calibrated dual-residue analog to digital converter in 90 nm CMOS

Zjajo, Amir; Gyvez, José Pineda de

doi:10.1109/islped.2011.5993634

Cited by 3 publications

(2 citation statements)

References 31 publications

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“…The proposed monitors and algorithms are evaluated on a 12-bit A/D converter described in [19] (Fig. 7) and fabricated in a standard single poly six-metal 90-nm CMOS (Fig.…”

Section: Resultsmentioning

confidence: 99%

Low-Power Die-Level Process Variation and Temperature Monitors for Yield Analysis and Optimization in Deep-Submicron CMOS

Zjajo

Barragán

Gyvez

2012

IEEE Trans. Instrum. Meas.

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Abstract-This paper reports design, efficiency, and measurement results of the process variation and temperature monitors for yield analysis and enhancement in deep-submicron CMOS circuits. Additionally, to guide the verification process with the information obtained through monitoring, two efficient algorithms based on an expectation-maximization method and adjusted support vector machine classifier are proposed. The monitors and algorithms are evaluated on a prototype 12-bit analog-todigital converter fabricated in standard single poly six-metal 90-nm CMOS.

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“…The proposed monitors and algorithms are evaluated on a 12-bit A/D converter described in [19] (Fig. 7) and fabricated in a standard single poly six-metal 90-nm CMOS (Fig.…”

Section: Resultsmentioning

confidence: 99%

Low-Power Die-Level Process Variation and Temperature Monitors for Yield Analysis and Optimization in Deep-Submicron CMOS

Zjajo

Barragán

Gyvez

2012

IEEE Trans. Instrum. Meas.

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“…Another approach would be to embed an analog-to-digital converter to generate a digital signature based on the voltage level at V DD _CC. This alternative, however, can be costly in terms of area, depending on the targeted precision, and also sensitive to process variations [11].…”

Section: Introductionmentioning

confidence: 99%

A built-in scheme for testing and repairing voltage regulators of low-power srams

Zordan

Bosio

Dilillo

et al. 2013

2013 IEEE 31st VLSI Test Symposium (VTS)

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Voltage regulation systems offer an efficient mechanism for reducing static power consumption of SRAMs. When the SRAM is not accessed for a long period, it switches into an intermediate low-power mode. In this mode, a voltage regulator is used to reduce the voltage supplied to the core-cell array as low as possible without data loss. Therefore, reliable operation of such device must be ensured by using adequate test techniques. In this work, we propose low area overhead built-in self-test (BIST) and built-in self-repair (BISR) schemes that can be embedded on the SRAM to automatically test and repair the voltage regulator. Simulation results prove the effectiveness of the proposed technique for detecting, diagnosing and repairing voltage regulators of low-power SRAMs.Index Terms-SRAM, low-power design, design for testability, memory test.

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Circuit Solutions

Zjajo¹

2013

Stochastic Process Variation in Deep-Submicron CMOS

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A 1.2V 55mW 12bits self-calibrated dual-residue analog to digital converter in 90 nm CMOS

Cited by 3 publications

References 31 publications

Low-Power Die-Level Process Variation and Temperature Monitors for Yield Analysis and Optimization in Deep-Submicron CMOS

Low-Power Die-Level Process Variation and Temperature Monitors for Yield Analysis and Optimization in Deep-Submicron CMOS

A built-in scheme for testing and repairing voltage regulators of low-power srams

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