A 4Gb/s half-rate DFE with switched-cap and IIR summation for data correction

Jeon, Gyunam; Kim, Yong-Bin

doi:10.1109/iscas.2017.8050891

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Proposed Dfe Architecture1

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2021

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Cited by 2 publications

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“…A typical DFE has summers depending on the number of interleaves (shown as a gray line in Fig. 2) [4,18,19,20,23,24,25]. The proposed DFE halves the number of summers by using resettable slicer and summer with multiplexer.…”

Section: Proposed Dfe Architecturementioning

confidence: 99%

A 0.88-pJ/bit 28Gb/s quad-rate 1-FIR 2-IIR decision feedback equalizer with 21dB loss compensation in 65nm CMOS process

Kang

Song

2021

IEICE Electron. Express

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This paper describes quad-rate 1-FIR 2-IIR decision feedback equalizer (DFE) with summer reduction technique for high-speed serial communication in a 65nm CMOS technology. The proposed DFE halves the number of summers by using resettable slicer and summer with multiplexer. Therefore, the proposed DFE reduces power consumption significantly because summer dissipates a lot of power. The DFE that is verified by pre-layout simulations achieved 0.69 unitinterval (UI) eye-opening. The proposed DFE that is designed with a 65-nm technology operates at 28Gb/s and occupies 0.023mm 2 . Finally, the power efficiency of the proposed DFE is 0.88-pJ/bit.

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