A 48 dBm peak power RF switch in SOI process for 5G mMIMO applications

Malladi, Venkata N.K; Miller, M.E.

doi:10.1109/sirf.2019.8709096

Cited by 8 publications

(5 citation statements)

References 1 publication

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“…Table III compares the electrical performance of high power switches designed by stacked FETs technology. Compared with the work in [30], this work shows close insertion loss and better P-0.1dB. Besides, this work does not require negative voltage to provide sufficient supply voltage difference, which is more space-saving for the terminal applications.…”

Section: Experiments Resultsmentioning

confidence: 93%

A low-supply-voltage high-power-handling stacked SPDT switch based on feedforward capacitors

Shen,

Li,

Jin

et al. 2023

IEICE Electron. Express

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In this letter, a 30MHz-3GHz 10W single pole double throw (SPDT) switch with 3.3V low supply voltage fabricated in 0.5um GaAs pHEMT technology process is presented. A feedforward capacitor pair is introduced in each stacked FET, which makes full use of the advantages of high breakdown voltage (VBDG) of GaAs process under low supply voltage and enhances the power handling of each FET unit. Under specific power level, switch with reduced number of stacked FETs and low insertion loss are achieved. Meanwhile, uniform-partial-voltage stacked FET units with different gate width is applied to the switch design, which solves the problem of non-uniform partial voltage caused by parasitic capacitance(Cpd) between stacked FETs. As a result, the power handling of the switch is higher than 40dBm under continuous wave. Besides, the switch designed in this letter achieves 0.5dB insertion loss at 1.5GHz and the input and output return loss is less than -18dB at the whole frequency band. The test results verify the accuracy of the theoretical analysis.

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Section: Experiments Resultsmentioning

confidence: 93%

A low-supply-voltage high-power-handling stacked SPDT switch based on feedforward capacitors

Shen,

Li,

Jin

et al. 2023

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…As shown in Fig. 1(a), the conventional structure has been used a floating gate/body [4], negative biasing [5], and stacked-FET [6], [7], [8]. However, to handle a high-power while using conventional structure, these techniques use large value gate resistors (R G ) and common gate resistor (R GC ).…”

Section: Design Concept a Switching Time Analysis Of Typical High-pow...mentioning

confidence: 99%

High-Powered RF SOI Switch With Fast Switching Time for TDD Mobile Applications

Seo

Kim

et al. 2023

IEEE Access

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This paper presents a fast switching and high-powered single-pole double-throw (SPDT) switch for RF switch circuits, such as TRx antenna switches and frequency band (or operation mode) selection switches in mobile handset applications. For fast switching time and performances of the RF switch, we proposed a novel method that can ''selectively'' control the impedance of a gate biasing circuit (''high'' or ''low'' impedance). The proposed SPDT switch use the low impedance of the gate biasing circuit for fast switching time and use the high impedance of the gate biasing circuit to avoid the degradation of the insertion loss and harmonics. The proposed SPDT switch has no additional bias and no large payment for size consumption. According to measurement results, the turn-on switching time of the proposed SPDT switch was 0.35 µs (at 2 GHz). The insertion loss, isolation, and return loss at 2 GHz were 0.16 dB, 47.1 dB, and 24 dB respectively. 2nd and 3rd harmonic levels at 25 dBm input power at 2 GHz were −88.7 dBm and −78.9 dBm, respectively. Power handling capability was 39.5 dBm of input power at 2 GHz. The designed SPDT switch was implemented in a 0.13-µm partially depleted silicon-on-insulator (PD-SOI) process.INDEX TERMS Fast switching time, high-power handling, partially depleted silicon-on-insulator (PD-SOI), RF switch, single-pole double-throw (SPDT).

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“…For the case of the CMOS SOI switch with a single-branch structure based on multi-stacked FET, it has the advantage of improving the power handling capability compared to that of the two cases mentioned above, due to the mitigated drain-source voltage (V ds.Mn ) of the single-FET, as shown in Figure 2 [4][5][6][7]. If the shunt branch is in the off-state condition, single-FETs are considered to be a simple capacitive equivalent circuit composed of symmetrical parasitic capacitances ('C gs ≈ C gd ' and 'C bs ≈ C bd ') between each node because of the symmetrical drain-source structure and floating gate/body condition, which is implemented by the gate/body resistors (R G , R B , R GC , R BC ) of tens of kilo-ohm or more (see Figure 2).…”

Section: Power Handling Capability and Linearity Of The Tunermentioning

confidence: 99%

A Programmable Impedance Tuner with a High Resolution Using a 0.18-um CMOS SOI Process for Improved Linearity

2019

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In this paper, a novel coupler/reflection-type programmable electronic impedance tuner combined with switches that were fabricated by a 0.18-um complementary metal–oxide–semiconductor (CMOS) silicon-on-insulator (SOI) process is proposed for replacement of the conventional mechanical tuner in power amplifier (PA) load-pull test. By employing the multi-stacked field-effect transistors (FETs) as a single-branch switch, the proposed tuner has the advantage of precise impedance variation with systematic and magnitude and phase adjustment. Additionally, it led to high standing wave ratio (SWR) coverage and a good impedance resolution with a high power handling capability. Furthermore, the double-branch based on multi-stacked FET was applied to switches for additional enhancement of the intermodulation distortion (IMD) performance through the mitigated drain-source voltage of the single-FET. Drawing upon the measurement results, we demonstrated that SWR changed from 2 to 6 sequentially with a 12–15° phase angle step over a mid/high-band range of a 1.5–2.1 GHz band for 3G/4G handset application. In addition, the PA load-pull measurement results obtained using the proposed tuners verified their practicality and competitive performance with mechanical tuners. Finally, the measured linearity using the double-branch switch demonstrated the good IMD3 performance of −78 dBc, and this result is noteworthy when compared with conventional electronic impedance tuners.

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A 48 dBm peak power RF switch in SOI process for 5G mMIMO applications

Cited by 8 publications

References 1 publication

A low-supply-voltage high-power-handling stacked SPDT switch based on feedforward capacitors

A low-supply-voltage high-power-handling stacked SPDT switch based on feedforward capacitors

High-Powered RF SOI Switch With Fast Switching Time for TDD Mobile Applications

A Programmable Impedance Tuner with a High Resolution Using a 0.18-um CMOS SOI Process for Improved Linearity

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