A 45ns 16 × 16 CMOS multiplier

This paper describes recent progress in the implementation of a high speed Fast Fourier Transform (FFT) processor with state-of-the-art VLSI circuits. Initial efforts have produced FFT and inverse FFT processors that operate at data rates of up to 40 MHz (complex). The current implementation computes transforms of up to 16,384 points in length by means of the McClellan and Purdy radix 4 pipeline FFT algorithm.The arithmetic is performed by single chip 22 bit floating point adders and multipliers, while the interstage reordering is performed by delay commutators implemented with semi-custom VLSI. This paper explains the pipeline FFT implementation and focuses attention on our current activity which involves developing a fixed point arithmetic version using CMOS multipliers and adders to reduce the power consumption.

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“…We are implementing 16 bit fixed point arithmetic which allows use of the recently announced CMOS 16 bit multipliers (ref. 10,11).…”

Section: The Delay Commutator Circuitmentioning

confidence: 99%

High Speed FFT Processor Implementation

Swartzlander

Stroll

1984

MILCOM 1984 - IEEE Military Communications Conference

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“…Especially in pipeline schemes which are key technology of high speed processing, the parallel high speed multiplier is extremely suitable. Thus a lot of parallel multipliers have been reported as shown in Table 1[3] [4][5] [6] [7]. This paper describes a 32 X 32-bit parallel multiplier as developed for a macro cell.…”

Section: Introductionmentioning

confidence: 99%

A 15 ns 32&amp;times;32-bit CMOS multiplier with an improved parallel structure

Nagamatsu

Tanaka

Mori

et al. 1989

1989 Proceedings of the IEEE Custom Integrated Circuits Conference

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A 32 X 32-bit parallel multiplier with an improved parallel structure has been fabricated by 0.8 pm CMOS triple level metal interconnections technology. A new unit adder which can sum up 4 partial products concurrently has been developed. It enhances the parallelism of multiplier. The chip contains 27704 transistors with 2.68 X 2.71 mm2 die area. The multiplication time is 15 ns at 5 volt power supply. The power dissipation is 277 mW at 10 MHz operations.

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