The design of a testable parallel multiplier

Hong, S.J.

doi:10.1109/12.48874

Cited by 9 publications

(3 citation statements)

References 6 publications

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“…Reference [1] uses 6 extra pins and 16 patterns getting 100 percent test coverage, while [2] uses 7 extra pins and 8 test patterns. Reference [3] modifies the multiplier and use only 1 extra pin, but it gets a linear-testable module. All these need to change the design, and it may introduce performance issues.…”

Section: Introductionmentioning

confidence: 99%

Instruction level test for parallel multipliers

Ma¹,

Gao

2008

2008 15th IEEE International Conference on Electronics, Circuits and Systems

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Multiplication operations are the normal operations in operating systems or scientific calculations. Multipliers embedded in processors, DSP or SoC are well optimized for best performance, and they are sensitive to test overhead. Instruction level test is a popular functional test approach for microprocessors test, and it can get satisfactory test results. But for the multipliers, one important part of microprocessors, there is no detail on how to testing them. This paper presents an instruction level test approach for the multiplier test. The proposed approach does not modify the multipliers and does not need any extra logic just using instructions of the processors to test processors' multipliers. Sequentially it does not have any test cost on area or timing. Moreover the instruction-level test is suited for at-speed test in nature. Experimental results on the real processor's circuits show that the instruction level test approach has good effect on parallel multipliers

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Section: Introductionmentioning

confidence: 99%

Instruction level test for parallel multipliers

Ma¹,

Gao

2008

2008 15th IEEE International Conference on Electronics, Circuits and Systems

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“…The problem of testing one-dimensional and two-dimensional arrays for single faults has been studied extensively 1,2,3,4,5,6,7,8] with considerable attention on arithmetic circuits. Researchers have modi ed the array multiplier to make it C-testable 2], that is, testable with a constant number of tests independent of the size of the array multiplier 9, 7,10]. Under the single faulty cell model it is assumed that at most one cell is faulty, and the fault may alter the cell's output function in any arbitrary way, as long as the cell remains combinational and the fault is permanent.…”

Section: Introductionmentioning

confidence: 99%

Detection of multiple faults in two-dimensional ILAs

Schlag

Ferguson

1996

IEEE Trans. Comput.

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We provide test sets proportional to the sum of the two dimensions of the array for a large class of cells, which allow us to test rows (or columns) of cells of the array independently. Constant length test sets for array multipliers have been found under the single faulty cell model if the array is modi ed and otherwise test sets are proportional to the number of cells. We can verify the full adder array of a combinational n m multiplier in O(n + m) tests under the Multiple Faulty Cell (MFC) model. The entire multiplier, including the AND gates which generate the summands, can be veri ed after applying the same modi cations which make the multiplier C-testable under the single faulty cell model.

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“…a C-testable [12], has the constant size of test pattern sets. The Design-forTestability methods and a comprehensive study of testability of multipliers have been discussed in detail in [13][14][15][16] where various fault models of different test pattern set size and variant hardware requirement have been studied. High fault coverage of multipliers is achieved with Cell Fault Model [17].…”

Section: Previous Workmentioning

confidence: 99%

Universal Pattern Set for Arithmetic Circuits

Kumar¹,

Choudhary²,

Bhardwaj³

et al. 2012

IJCA

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The exponential increase in test cost is one of the new challenges being posed by technology scaling. This Paper has been aimed to deal with the issue of testing cost which adds to the chip cost. Here we propose a new pattern set for testing the arithmetic circuits which contains a minimum number of test vectors and easy to generate on the chip and hence supports at-speed testing of the circuit. Though maximum fault coverage is desired but practically generation of test vectors for testing of all the possible defects is not at all feasible. This leads to the modeling of defects as faults which facilitate for simplification of test generation process. Though various fault models have been proposed, the single stuck-at fault model is one of widely accepted model because of having closeness to the actual defects and also, it provide the algorithmic possibilities which, further helps in generation of test vectors. The desired smaller DPM (defective parts per million) levels for devices, creates the need for application of better fault models, which can model the defects in the most accurate fashion. This result in complex fault models which tends to make test generation tedious or even impossible and ultimately increase the test cost. Our motive is to cut down the test cost by finding the minimal number of test vectors for the test. If reduction in the patterns for one module is achieved, it would reduce the overall test cost. We propose universal pattern set which gives good fault coverage for arithmetic circuit with small set of vectors.

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The design of a testable parallel multiplier

Cited by 9 publications

References 6 publications

Instruction level test for parallel multipliers

Instruction level test for parallel multipliers

Detection of multiple faults in two-dimensional ILAs

Universal Pattern Set for Arithmetic Circuits

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