A 45nm Self-Aligned-Contact Process 1Gb NOR Flash with 5MB/s Program Speed

Javanifard, J.; Tanadi, T.; Giduturi, H.; Loe, K.; Melcher, R. L.; Khabiri, S.; Hendrickson, N.; Proescholdt, A.; Ward, D.A.; Taylor, M A

doi:10.1109/isscc.2008.4523238

Cited by 21 publications

(13 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In this section, we present the conventional sensing circuit and the latch sense amplifier for STT-RAM, which include a source degeneration sensing circuit (SDSC) [12] with equalizing transistors [29] and voltage-latched sense amplifier with double switches and transmission gate (TG) access transistors (DSTA-VLSA) [25]. In addition, the OC-VLSA [23], which is the previous latch offset cancellation sense amplifier, is presented. Fig.…”

Section: Introductionmentioning

confidence: 99%

“…Fig. 2 shows the concept and circuit of the OC-VLSA, which cancels [23]. The OC-VLSA requires four phases to cancel : precharge phase in which C1 and C2 are precharged to , offset nulling phase in which C1 and C2 are discharged to each threshold voltage of M3 and M4, voltage-capturing phase in which the developed and by SDSC are applied to the gate of the latching transistors (M1-M4), and comparison phase in which is compared regardless of the mismatch between M3 and M4.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Latch Offset Cancellation Sense Amplifier for Deep Submicrometer STT-RAM

Song

Kim

et al. 2015

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

As technology node shrinks, spin-transfer-torque random access memory (STT-RAM) has become a promising memory solution owing to its great scalability. However, the increase in process variation and decrease in the supply voltage result in the degradation of the read yield; thus, achieving the target read yield is an important issue in a deep-submicrometer technology node. In this paper, we propose a latch offset cancellation sense amplifier (LOC-SA) that cancels the latch offset with a compact area by merging the sensing circuit, latch sense amplifier, and write driver. By virtue of the latch offset cancellation characteristic, the voltage developing time can be significantly saved, leading to sensing-speed improvement. The Monte Carlo HSPICE simulation results using industry-compatible 45-nm model parameters show that the LOC-SA satisfies a target read yield of six-sigma (96.74% for 32 Mb) with more than 2 faster sensing speed, 1.12 lower read energy, and 1.13 smaller area when compared with the best value of design parameters of other sense amplifiers.Index Terms-Latch sense amplifier, MRAM, offset cancellation technique, read access pass yield, STT-RAM.

show abstract

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Latch Offset Cancellation Sense Amplifier for Deep Submicrometer STT-RAM

Song

Kim

et al. 2015

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

show abstract

“…Most eFlash macros employ current-mode sense amplifiers (CSA) instead of voltage-mode sense amplifiers (VSA) due to their fast read speeds when dealing with a small read cell current (I CELL ) on a long bitline (BL) [4], [5]. However, previous CSAs have yet to achieve high-speed read operations due to the following: 1) large summed read-path input offsets (I OS-SUM ) caused by fluctuations in BL bias, CSA device mismatch, and reference current (I REF ) variation [4], [6]; 2) small difference in I CELL ( I CELL = I CELL0 -I CELL1 ) between erased (I CELL0 ) and programmed cells (I CELL1 ) due to wide tail-bit distribution; and 3) the need for long BL precharge/settling time (T PRE ) to provide I CELL sufficient to overcome 1) and 2). An insufficient T PRE increases I OS-SUM and reduces I CELL , resulting in read failure.…”

Section: Introductionmentioning

confidence: 99%

An embedded flash macro with sub-4ns random-read-access using asymmetric-voltage-biased current-mode sensing scheme

Liu

Chang

Lin

et al. 2013

2013 IEEE Asian Solid-State Circuits Conference (A-Sscc)

View full text Add to dashboard Cite

High-performance mobile chips and MCUs require large-capacity and fast-read embedded nonvolatile/Flash memory (eNVM/eFlash) for code and data storage. Current-mode sense amplifiers (CSA) are commonly used in eNVM due to their fast sensing against large bitline (BL) load and small cell read currents. However, conventional CSAs cannot achieve fast random read access time (T AC ) due to significant summed readpath input offsets (I OS-SUM ). This work proposes an asymmetricvoltage-biased CSA (AVB-CSA) to suppress I OS-SUM and enable high-speed sensing without run-time offset-cancellation operations. A 90nm AVB-CSA 1Mb Flash macro with BL-length test-modes was fabricated. The 512-rows AVB-CSA eFlash macro achieves 3.9ns T AC . The test-mode experiments confirmed that AVB-CSA improves 1.48x in T AC for 2048-rows BL-length. For the first time, a Mb eFlash with long BL achieves sub-4ns T AC .

show abstract

“…Cascodecurrent-load or resistive-divider-like CSAs (RD-CSAs) [1], [5], achieve sub100nA sensing, but require long BL settling times to achieve high-accuracy 1 ststage voltage difference. The inverter-offset-compensated SA (IOC-SA) [6] reduces the SA offset. However, BL offset and BL settling time still limits its advantages with regard to VSA/CSA.…”

mentioning

confidence: 99%

An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory

Chang

Shen

Liu

et al. 2011

2011 IEEE International Solid-State Circuits Conference

View full text Add to dashboard Cite

Decreasing read cell current (I CELL ) has become a key trend in nonvolatile memory (NVM). This is not only due to device size and V DD scaling while keeping the same threshold voltage (V TH ), but also to the growing spread of the following applications: 1) multiple-level-cell (MLC) [1-2] to achieve smaller area-per-bit; 2) lower-V DD [3] to save power consumption; 3) Logic-process-compatible onetime programming memories (OTP) for embedding into mobile chips. A smaller I CELL leaves the sense amplifiers (SAs) operation vulnerable to 1) bitline (BL) level offset due to noise, bias and load (C BL ) mismatches and 2) V TH variation. As device size and BL-pitch is continually scaled down, the above factors have become major showstopper for SAs. To tolerate these offsets, small-I CELL NVMs suffer from slow read speed or high read fail probability. Thus, a more largely offset tolerant SA is a prerequisite to achieve faster read speeds. In this study, we propose a new offset tolerant current-sampling-based SA (CSB-SA) to achieve 7× faster read speed than previous SAs for sensing small I CELL . A fabricated 90nm 512Kb OTP macro, using the CSB-SA and our CMOS-logiccompatible OTP cell [4], achieves 26ns macro random access time for reading sub-200nA I CELL . Measurements also confirmed that this 90nm CSB-SA could achieve sub-100nA sensing.Many small-I CELL NVMs employ voltage-mode SA (VSA) [2] with a long BL developing time to tolerate SA offset, at the cost of a reduced read speed. Current-mode SA (CSA) achieves faster read speeds than VSA [1]. Cascodecurrent-load or resistive-divider-like CSAs (RD-CSAs) [1], [5], achieve sub100nA sensing, but require long BL settling times to achieve high-accuracy 1 ststage voltage difference. The inverter-offset-compensated SA (IOC-SA) [6] reduces the SA offset. However, BL offset and BL settling time still limits its advantages with regard to VSA/CSA. In comparison with I CELL and a referencecurrent (I REF ), current-mirror CSA (CM-CSA) [7], has fast read speeds but cannot sense small I CELL due to its input-stage V TH mismatch. Figure 11.5.1 compares the concepts of CSB-SA with previous SAs. CSB-SA uses the same MOS device for current sampling and current-ratio amplifying. This enables V THindependent current sampling schemes for its differential I CELL and I REF inputs. This is significantly different from CM-CSA, using different MOS devices for current-mirroring or I-V conveying, which results in increased vulnerability to V THmismatch. In addition, CSB-SA uses sampled current to generate fast 1 st -stage voltage difference at its BL-decoupled small-load internal nodes. Unlike VSA or RD-CSA, which have to develop their 1 st -stage voltage on the heavy-load BL using continuous I CELL driving. IOC alleviates SA V TH -mismatch but with a complex multi-step V TH -nulling process and numerous switching devices. IOC also does not cancel the SA offset due to transistor width/length or T OX variations, and is still vulnerable to BL noise/C BL mismatch. In our CSB-SA, the sampled currents a...

show abstract

A 45nm Self-Aligned-Contact Process 1Gb NOR Flash with 5MB/s Program Speed

Cited by 21 publications

References 4 publications

Latch Offset Cancellation Sense Amplifier for Deep Submicrometer STT-RAM

Latch Offset Cancellation Sense Amplifier for Deep Submicrometer STT-RAM

An embedded flash macro with sub-4ns random-read-access using asymmetric-voltage-biased current-mode sensing scheme

An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory

Contact Info

Product

Resources

About