A 45-Mbits/sec. VLSI Viterbi decoder for digital video applications

Edwards, G.D.

doi:10.1109/ntc.1993.292997

Cited by 4 publications

(2 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Accordingly, several in-depth studies of its implementation in digital communication and storage devices have been carried out over the last decades [2]. Although the previous works have standardized the Viterbi decoder architecture [3], [4], the demands for low-area and low-power hardware is consistently increasing. In the Viterbi decoder, static random access memories (SRAMs) are widely used as embedded memories.…”

Section: Introductionmentioning

confidence: 99%

“…To achieve sufficient error correcting performance, the memory size of the Viterbi decoder should be large enough to satisfy the required traceback depth. In recent communication systems such as IEEE 802.11n, the traceback depth is typically set to 6 times the constraint length (K) for unpunctured codes, and up to 15 times of K for highly punctured codes [3]. Due to this requirement, the area and power consumption of the embedded memories in the Viterbi decoder have been continuously increasing.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Refresh-Less eDRAM Macro With Embedded Voltage Reference and Selective Read for an Area and Power Efficient Viterbi Decoder

Choi

Kang

2015

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

This paper presents a Viterbi-specific 2T gain cellbased embedded DRAM (eDRAM) design for IEEE 802.11n WLAN application. In the proposed Viterbi decoder, refresh operations are completely removed in the eDRAM, by ensuring that the read-after-write period of survivor memory is shorter than the retention time of the gain cell. In order to facilitate the write operation with single-supply voltage, a beneficial read word-line (RWL) coupling technique is proposed. In this work, we also present a reference voltage generation scheme to support single-ended read operation. Thanks to the decoupled read and write structure of the gain cell, the proposed eDRAM can support dual-port operations without large area overhead, thus doubling the bandwidth of memories in the Viterbi decoder. To further reduce the area of the customized Viterbi memory, common redundant hardware between the memory peripheral and computational logics is identified and eliminated without latency overhead. The 4 bit soft-decision 64-state Viterbi decoder with 24 kb eDRAM (1-bank) is implemented in 65 nm CMOS process technology. The chip measurement results show 44% area and 39% power savings over the conventional SRAM-based Viterbi decoder implementation.

show abstract

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%