A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption

Yoshida, Yutaka; Kamei, Takeshi; Hayase, K.; Shibahara, Shinichi; Nishii, O.; Hattori, Toshihiro; Hasegawa, Atsushi; Takada, Masashi; Irie, Naohiko; Uchiyama, Kunio; Odaka, Takahiro; Takada, K.; Kimura, Keiji; Kasahara, Hironori

doi:10.1109/isscc.2007.373607

Cited by 27 publications

(13 citation statements)

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“…However, we use a development board RP1 [23] that is somehow similar to the LLM machine architecture. RP1 is equipped with a quad-core SH-4A processor and for each core, it has a user memory region that can be seen as the local memory, which can meet major requirements of the LLM machine architecture.…”

Section: B Research Platformmentioning

confidence: 99%

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Local-Memory-Based Integrity Checking for Embedded Systems

Nakajima

2013

2013 IEEE 16th International Conference on Computational Science and Engineering

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The Limited Local Memory (LLM) machine architecture is proposed to improve the security on a multi-core processor with a small trusted computing base (TCB). It uses one privileged core's local memory for executing detection tools to monitor the state of a target OS running on other cores, depending on isolation of the privileged core to ensure the reliability of the detection tools. It has some characteristics fitting embedded systems, such as causing little overhead, a small TCB and requiring minimal modification on the target OS. However, in current research, the LLM architecture was only emulated in QEMU, a virtual machine monitor, and assumed a limited and somehow big space of the local memory that may rarely be equipped on embedded processors.In this paper, we apply this method to a real embedded platform with a LLM-similar hardware configuration, but equipped with a much smaller local memory. Firstly, we propose design details to apply our system to a local memory with such a small size. Then we evaluate the influence that this method would cause to the detection tools and present some hardware recommendations to make the LLM architecture more applicable on real processors. Our research can illustrate the efficiency of the LLM architecture and generalize the application of it for embedded systems by reducing the size requirement on the local memory.

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Section: B Research Platformmentioning

confidence: 99%

“…It is hard to consider that there is so much private memory space for cores in embedded processors. For example, RP1 [23] and Cell B.E. [24] have a local-memory-similar architecture with respective size of 128 Kbytes and 256 Kbytes.…”

Section: Introductionmentioning

confidence: 99%

Local-Memory-Based Integrity Checking for Embedded Systems

Nakajima

2013

2013 IEEE 16th International Conference on Computational Science and Engineering

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“…2) Implementation for multi-core processor: We implement this multi-thread model for fine-grain parallelization on the multi-core processor named RP1 [12]. Table I lists RP1 specifications.…”

Section: Evaluation Using Multi-core Processormentioning

confidence: 99%

Proposal of a multi-core processor from the viewpoint of evolutionary computation

Sato

Namiki

2010

IEEE Congress on Evolutionary Computation

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The use of low-cost multi-core processors that target small-scale parallelism of several or several tens of processing units has recently spread to general-purpose personal computers. As part of this trend, research on converting evolutionary computation to parallel processing on multi-core processors has begun. In our research, we place importance on proposing multi-core processor architectures from the viewpoint of evolutionary computation and on proposing indices for identifying chips that exhibit high affinity with evolutionary computation from among existing multi-core processors. This paper takes a first step in this direction by focusing on local memory built into a multi-core processor and proposing a specification that allows the contents of local memory in any core to be directly accessed by any other core without using main memory. We describe a desktop comparison with singlecore processors and general multi-core processors and show that a speed-up effect should be expected with the proposed specification for both fine-grain and coarse-grained parallelization techniques. We also describe an evaluation on actual multicore processor for the case of fine-grain parallelization and show that the speed-up effect is also useful in reducing energy consumption.

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“…Microcontroller vendors like IBM, ARM, Fujitsu and Renesas have announced different multicore processors and SoCs [5][6][7][8] for embedded systems. The advantages of using multicore processors in embedded systems can be simply summarized into two points.…”

Section: Introductionmentioning

confidence: 99%

Elliptic curve cryptography on embedded multicore systems

Fan

Sakiyama

Verbauwhede

2008

Des Autom Embed Syst

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The increasing use of network-connected embedded devices and online transactions creates a growing demand of network security for embedded systems. The security requirements, such as authentication, confidentiality and integrity, always make computationally intensive processes and can easily become the bottleneck of the related applications. In this paper we implement an embedded multicore system, and explore the task scheduling methods in different levels. First, we propose an instruction scheduling method that utilizes all the cores to perform one modular operation in parallel. Second, we perform multiple modular operations with multiple cores in parallel. The performance of those two implementations is compared and a scheduling method combining these two types of parallelism is proposed. We discuss the details of our proposed method by using an FPGA implementation of ECC over a prime field.

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A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption

Cited by 27 publications

References 1 publication

Local-Memory-Based Integrity Checking for Embedded Systems

Local-Memory-Based Integrity Checking for Embedded Systems

Proposal of a multi-core processor from the viewpoint of evolutionary computation

Elliptic curve cryptography on embedded multicore systems

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