A 40nm 16-core 128-thread CMT SPARC SoC processor

Shin, Jinuk Luke; Tam, Kenway W.; Huang, Dawei; Petrick, Bruce; Pham, Ha; Hwang, Chul Ju; Li, Hongping; Smith, Alan; Johnson, Timothy; Schumacher, Francis; Greenhill, D.; Leon, Ana Sonia; Strong, Allan

doi:10.1109/isscc.2010.5434030

Cited by 63 publications

(36 citation statements)

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“…All experiments are carried out in the above mentioned presently-shipping enterprise server, which contains two SPARC T3 processors [23] in 2 sockets that provide a total of 256 hardware threads, 32 8GB memory DIMMs, and 2 hard drives. We enable customized fan control by setting the fan currents through external Agilent E3644A power supplies, as shown in Figure 2.…”

Section: Methodsmentioning

confidence: 99%

Leakage-Aware Cooling Management for Improving Server Energy Efficiency

Zapater

Tuncer

Ayala

et al. 2015

IEEE Trans. Parallel Distrib. Syst.

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Abstract-The computational and cooling power demands of enterprise servers are increasing at an unsustainable rate. Understanding the relationship between computational power, temperature, leakage, and cooling power is crucial to enable energy-efficient operation at the server and data center levels. This paper develops empirical models to estimate the contributions of static and dynamic power consumption in enterprise servers for a wide range of workloads, and analyzes the interactions between temperature, leakage, and cooling power for various workload allocation policies. We propose a cooling management policy that minimizes the server energy consumption by setting the optimum fan speed during runtime. Our experimental results on a presently shipping enterprise server demonstrate that including leakage awareness in workload and cooling management provides additional energy savings without any impact on performance.

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Section: Methodsmentioning

confidence: 99%

Leakage-Aware Cooling Management for Improving Server Energy Efficiency

Zapater

Tuncer

Ayala

et al. 2015

IEEE Trans. Parallel Distrib. Syst.

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“…Beyond utilization, both schemes significantly improve throughput for batch applications. In-order cores: Many datacenter workloads have vast requestlevel parallelism, so using simpler cores can be a sensible way to improve datacenter efficiency [43,50,56]. To see if our proposed techniques apply to simpler cores, Figure 11 shows tail latencies and weighted speedups when using simple in-order core models (IPC=1 except on L1 misses) instead of OOO cores.…”

Section: Comparison Of Llc Management Schemesmentioning

confidence: 99%

Ubik

Kasture

Sánchez

2014

Proceedings of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems

114

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Chip-multiprocessors (CMPs) must often execute workload mixes with different performance requirements. On one hand, user-facing, latency-critical applications (e.g., web search) need low tail (i.e., worst-case) latencies, often in the millisecond range, and have inherently low utilization. On the other hand, compute-intensive batch applications (e.g., MapReduce) only need high long-term average performance. In current CMPs, latency-critical and batch applications cannot run concurrently due to interference on shared resources. Unfortunately, prior work on quality of service (QoS) in CMPs has focused on guaranteeing average performance, not tail latency.In this work, we analyze several latency-critical workloads, and show that guaranteeing average performance is insufficient to maintain low tail latency, because microarchitectural resources with state, such as caches or cores, exert inertia on instantaneous workload performance. Last-level caches impart the highest inertia, as workloads take tens of milliseconds to warm them up. When left unmanaged, or when managed with conventional QoS frameworks, shared last-level caches degrade tail latency significantly. Instead, we propose Ubik, a dynamic partitioning technique that predicts and exploits the transient behavior of latency-critical workloads to maintain their tail latency while maximizing the cache space available to batch applications. Using extensive simulations, we show that, while conventional QoS frameworks degrade tail latency by up to 2.3×, Ubik simultaneously maintains the tail latency of latency-critical workloads and significantly improves the performance of batch applications.

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“…As a result, most researchers still use sequential simulators and limit their studies to architectures with 16-32 cores. With chips that feature hundreds of threads and cores already on the market [45,48], developing simulation techniques that scale efficiently into the thousands of cores is critical.…”

Section: Introductionmentioning

confidence: 99%

ZSim

Sánchez

Kozyrakis

2013

Proceedings of the 40th Annual International Symposium on Computer Architecture

315

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Architectural simulation is time-consuming, and the trend towards hundreds of cores is making sequential simulation even slower. Existing parallel simulation techniques either scale poorly due to excessive synchronization, or sacrifice accuracy by allowing event reordering and using simplistic contention models. As a result, most researchers use sequential simulators and model small-scale systems with 16-32 cores. With 100-core chips already available, developing simulators that scale to thousands of cores is crucial.We present three novel techniques that, together, make thousand-core simulation practical. First, we speed up detailed core models (including OOO cores) with instructiondriven timing models that leverage dynamic binary translation. Second, we introduce bound-weave, a two-phase parallelization technique that scales parallel simulation on multicore hosts efficiently with minimal loss of accuracy. Third, we implement lightweight user-level virtualization to support complex workloads, including multiprogrammed, client-server, and managed-runtime applications, without the need for full-system simulation, sidestepping the lack of scalable OSs and ISAs that support thousands of cores.We use these techniques to build zsim, a fast, scalable, and accurate simulator. On a 16-core host, zsim models a 1024-core chip at speeds of up to 1,500 MIPS using simple cores and up to 300 MIPS using detailed OOO cores, 2-3 orders of magnitude faster than existing parallel simulators. Simulator performance scales well with both the number of modeled cores and the number of host cores. We validate zsim against a real Westmere system on a wide variety of workloads, and find performance and microarchitectural events to be within a narrow range of the real system.

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A 40nm 16-core 128-thread CMT SPARC SoC processor

Cited by 63 publications

References 1 publication

Leakage-Aware Cooling Management for Improving Server Energy Efficiency

Leakage-Aware Cooling Management for Improving Server Energy Efficiency

Ubik

ZSim

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