A 400-nW 19.5-fJ/Conversion-Step 8-ENOB 80-kS/s SAR ADC in 0.18- $\mu\hbox{m}$ CMOS

Cheong, Jia Hao; Chan, Kok Lim; Khannur, P.B.; Tiew, Kei Tee; Je, Minkyu

doi:10.1109/tcsii.2011.2158255

Cited by 42 publications

(16 citation statements)

References 4 publications

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“…In [18], an SAR ADC that utilizes a common mode resetting tri-level switching scheme and a time domain comparator with redundant algorithm is presented for applications like wearable sensor nodes and implantable medical devices powered by batteries or wireless charging, as shown in figure 7. The requirement of low power consumption has been achieved by reducing the static and switching power consumed by the ADC, where the switching activity and power is reduced by the proposed common mode resetting tri-level switching scheme and the time domain comparator has been used due to its low voltage operation ability and zero static power consumption.…”

Section: Successive Approximation +Register Adcmentioning

confidence: 99%

“…7. Tri-level switching based SAR ADC [18] [15] With the focus to reduce the battery lifetime, a power efficient Successive Approximation technique based ADC has been used to digitize the ECG signals acquired by the wavelet based ECG detector, for monitoring the heart-beat rate and its rhythm in a low power and energy efficient Implantable Pacemaker Integrated Circuit (IPIC) proposed in [19]. This SAR-ADC achieves lower power consumption by using voltage scaling and clock gating technique.…”

Section: Successive Approximation +Register Adcmentioning

confidence: 99%

See 1 more Smart Citation

Feasibility of Successive Approximation Register ADC in Ultra Low Power Biomedical Applications

Ahmed¹,

Bashir²,

Bilal³

et al. 2017

IJET

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Abstract-Analog-to-Digital Converter (ADC) is a critical block of the sensing unit of an implant and for measurements of various biophysiological signals, such as Electrocardiogram (ECG), Electroencephalogram (EEG) and Electromyogram (EMG) that covers the distinct portions of the frequency spectrum and signal bandwidths. ADC consumes about 30~35% of the total power of the device which is very high. Hence, for biomedical implants which require ultra low power consumption and low complexity to reduce the size and cost of the devices, there is a need of energy-efficient ADCs that conform to these restraints. This paper presents a study on the feasibility of ultra low power Successive Approximation Register (SAR) ADC in these biomedical applications. Various SAR ADC architectures proposed in the past decade to achieve ultra low power consumption have been investigated and their performances have been compared with respect to the parameters such as resolution, sampling frequency, signal-to-noise and distortion ratio, figure of merit among others. This paper also discusses the different switching schemes proposed to reduce the switching power consumed by the DAC. Finally, the future research scope and areas to further achieve ultra low power consumption without degrading the overall performance of the ADC has also been presented.

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Section: Successive Approximation +Register Adcmentioning

confidence: 99%

Section: Successive Approximation +Register Adcmentioning

confidence: 99%

Feasibility of Successive Approximation Register ADC in Ultra Low Power Biomedical Applications

Ahmed¹,

Bashir²,

Bilal³

et al. 2017

IJET

View full text Add to dashboard Cite

show abstract

“…Another technique is known as a generalized non-binary algorithm, where a non-integer ratio of capacitances is not needed [33], [43], [45][46][47], [52], [54], [58], [59], [61], [63], [65], [69]. For example, a non-binary weight such as {128, 46,26,20,14,8,6,4,2,1} instead of the binary weight of {128, 64,32,16,8,4,2,1} was used to obtain 8-bit resolution [69].…”

Section: B Circuit Implementationmentioning

confidence: 99%

Non-binary Successive Approximation Analog-to-Digital Converters: A Survey

Waho

2014

2014 IEEE 44th International Symposium on Multiple-Valued Logic

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Low-power successive-approximation (SA) analogto-digital converters (ADCs) are attracting increasing attention these days in biomedical and sensor network applications. The binary search algorithm is one of the basic idea behind how they obtain a binary code representing an analog input. In practice, the imperfectness of analog circuit elements sometimes results in decision errors and decreases the resolution of A/D conversion. Thus, making accurate decisions using imperfect elements is a big challenge. This paper surveys one solution known as non-binary SA with redundancy as well as related topics and its application to state-of-the-art SA ADCs.

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“…Trilevel switching reduces the switching energy and the total capacitance [4] and is widely used in SAR ADCs [4,5,6]. In the proposed calibration technique, the termination capacitor in the DAC is considered as a reference capacitor and the digital weights of all other unit capacitors are corrected with respect to the reference capacitor.…”

Section: Introductionmentioning

confidence: 99%

A digital background calibration technique for SAR ADC based on capacitor swapping

Ning

et al. 2014

IEICE Electron. Express

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A digital background calibration technique that compensates for capacitor mismatches is proposed for successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in the SAR ADC based on tri-level switching. The termination capacitor in the digital-to-analog converter is considered as a reference capacitor and the digital weights of all other unit capacitors are corrected with respect to the reference capacitor. Behavior simulation is performed to verify the proposed calibration technique by using a 12-bit SAR ADC with 3% random capacitor mismatch. The simulation result shows that the signal-to-noise and distortion ratio is improved from 57.1 dB to 72.0 dB and the spurious free dynamic range is improved from 62.0 dB to 82.6 dB.

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A 400-nW 19.5-fJ/Conversion-Step 8-ENOB 80-kS/s SAR ADC in 0.18- $\mu\hbox{m}$ CMOS

Cited by 42 publications

References 4 publications

Feasibility of Successive Approximation Register ADC in Ultra Low Power Biomedical Applications

Feasibility of Successive Approximation Register ADC in Ultra Low Power Biomedical Applications

Non-binary Successive Approximation Analog-to-Digital Converters: A Survey

A digital background calibration technique for SAR ADC based on capacitor swapping

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