A 400-MT/s 6.4-GB/s multiprocessor bus interface

Muljono, H.; Lee, Beomtaek; Tian, Yanmei; Wang, Yanbin; Atha, M.; Huang, Tian-Wei; Adachi, M.; Rusu, Stefan

doi:10.1109/jssc.2003.818295

Cited by 14 publications

(6 citation statements)

References 6 publications

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“…No termination resistors are required because driver directly matches the line impedance. In [6] a method for impedance matching is presented where line terminations are implemented with a combination of fixed resistors and variable dimension transistors. Variable dimension is achieved with a digitally controlled array of transistors.…”

Section: Conventional Approachmentioning

confidence: 99%

Automatic impedance control for chip-to-chip interconnections

Lopez-Delgadillo

Garcia-Andrade

Diaz-Mendez

et al. 2008

2008 15th IEEE International Conference on Electronics, Circuits and Systems

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Section: Conventional Approachmentioning

confidence: 99%

Automatic impedance control for chip-to-chip interconnections

Lopez-Delgadillo

Garcia-Andrade

Diaz-Mendez

et al. 2008

2008 15th IEEE International Conference on Electronics, Circuits and Systems

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“…6(b) are added. This proposed type uses both an NMOS diode for pulldown and a PMOS diode for pullup, whereas the previous types with a diode connection use only one between the pullup and pulldown; these types are usually used to control the slew-rate of the output signal [8], [9].…”

Section: Off-chip Drivermentioning

confidence: 99%

Voltage-Mode 1.5 Gbps Interface Circuits for Chip-to-Chip Communication

Lee¹,

Kim²,

Cho

et al. 2005

ETRI J

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In this paper, interface circuits that are suitable for point‐to‐point interconnection with an over 1 Gbps data rate per pin are proposed. To achieve a successful data transfer rate of multi‐gigabits per‐second between two chips with a point‐to‐point interconnection, the input receiver uses an on‐chip parallel terminator of the pass gate style, while the output driver uses the pullup and pulldown transistors of the diode‐connected style. In addition, the novel dynamic voltage level converter (DVLC) has solved such problems as the access time increase and valid data window reduction. These schemes were adopted on a 64 Mb DDR SRAM with a 1.5 Gbps data rate per pin and fabricated using a 0.10 µm dual gate oxide CMOS technology.

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“…Methods using I/O Loopback test has been proposed in [8]- [12]. I/O Loopback tests have a structure feeding the data captured at a receiver into the input flop at the transmitter through the output and input pads.…”

Section: Introductionmentioning

confidence: 99%

“…This method was extended to measure most I/O DC characteristics such as the output voltages and currents (VOL, IOL, VOH, IOH), the input voltage logic levels (VIL, VIH), and the pin leakage currents (IIL, IIH, IOZ) [9]. Additionally, the characterization of jitter and noise using I/O Loopback test has been proposed in [11], [12]. However, Loopback tests have a fault masking problem because the interface timing of inputs and outputs is measured jointly [13]; this would degrade the accuracy of testing.…”

Section: Introductionmentioning

confidence: 99%

A Built-In Self-Test scheme for high speed I/O using cycle-by-cycle edge control

Kim

Chung

Abraham

et al. 2010

2010 15th IEEE European Test Symposium

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This paper presents a Built-In Self-Test (BIST) circuit for high speed I/O, based on an embedded pattern generator to remove external factors which could affect the I/O parameters. The rising and falling edge positions of the generated patterns can be controlled independently during every cycle. In the basic operation mode, ATE provides the codes for controlling the edge positions, while in extended mode, an embedded counter generates the control codes. The control of both rising and falling edges makes this scheme especially good for systems with DoubleData Rate (DDR) interfaces. Moreover, the cycle-by-cycle control allows us to analyze efficiently the influence of mismatch trees and per-pin skew on I/O performance. The proposed BIST circuit has been simulated using a 0.18-µm process.

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A 400-MT/s 6.4-GB/s multiprocessor bus interface

Cited by 14 publications

References 6 publications

Automatic impedance control for chip-to-chip interconnections

Automatic impedance control for chip-to-chip interconnections

Voltage-Mode 1.5 Gbps Interface Circuits for Chip-to-Chip Communication

A Built-In Self-Test scheme for high speed I/O using cycle-by-cycle edge control

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