A 40% PAE Frequency-Reconfigurable CMOS Power Amplifier With Tunable Gate–Drain Neutralization for 28-GHz 5G Radios

Ali, Sheikh Nijam; Agarwal, Pawan; Renaud, Luke; Molavi, Reza; Mirabbasi, Shahriar; Pande, Partha Pratim; Heo, Deukhyoun

doi:10.1109/tmtt.2018.2801806

Cited by 57 publications

(15 citation statements)

References 21 publications

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“…Figure 11. CMOS power amplifier with a harmonic control circuit [17] In 2018, [18] proposed a high-efficiency frequency reconfigurable CMOS power amplifier (PA) design technique at 24 and 28 GHz using integrated tunable neutralization and matching networks as shown in Figure 12. Figure13(a) and (b) shows the circuit diagram of a conventional fixed coupling-coefficient transformer (kfixed) and the proposed reconfigurable coupling-coefficient transformer (krec), respectively.…”

Section: Ka Band Design Techniquementioning

confidence: 99%

Study of CMOS power amplifier design techniques for ka-band applications

Hasan¹,

Murad²,

Rani³

et al. 2019

IJEECS

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<span>This paper reviews of high efficiency CMOS power amplifiers (PAs) in millimeter (mm) wave Ka - Band applications. The study is focused on the challenges in designing PA especially in GHz frequencies inclusive of high gain, good input and output matching, efficiency, linearity, low group delay and low power consumption. Several works on CMOS PA from year 2009 to 2018 are discussed in this paper. Recent developments of CMOS PAs are examined and a comparison of the performance criteria of various techniques is presented.</span>

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Section: Ka Band Design Techniquementioning

confidence: 99%

Study of CMOS power amplifier design techniques for ka-band applications

Hasan¹,

Murad²,

Rani³

et al. 2019

IJEECS

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“…Electronics 2019, 8, x FOR PEER REVIEW 2 of 10 changed with process−voltage−temperature (PVT) variation and transistor model inaccuracy, the neutralization capacitor should also be made tunable to track the change of Cgd for an optimum neutralization effect. Previously, tunable neutralization was implemented using a varactor [13] and a switched inductor [14] at 60 GHz and 28 GHz, respectively. Nonetheless, they would suffer from high loss, transistor mismatch, and large chip area consumption.…”

Section: Conventional and Proposed Neutralization Techniquesmentioning

confidence: 99%

“…Those additional capacitors not only occupied an extra chip area, but also imposed additional loss, thus lowering the neutralization effect. In Reference [14], a switched inductor was employed for tunable neutralization. However, the inductor presented substantial parasitic capacitance, substrate loss, and chip area consumption.…”

Section: Conventional Neutralization Techniquesmentioning

confidence: 99%

“…Therefore, the neutralization does not suffer from capacitor loss, which tends to increase at high frequencies such as the W-band. Thirdly, the MOS-varactor occupies significantly less chip area and has a higher Q-factor at the W-band than the switched inductor employed in Reference [14]. Finally, since the MOS-varactor uses a similar structure and dimension as the main transistors, the neutralization is immune to mismatch caused by PVT variation.…”

Section: Implementation Of Mos−varactormentioning

confidence: 99%

“…Neutralization is one of the most popular techniques for improving both gain and stability [10][11][12][13][14]. An unwanted feedback through gate-to-drain capacitance (C gd ) of transistors is canceled by externally connecting a neutralization capacitor that offsets C gd [10][11][12].…”

Section: Introductionmentioning

confidence: 99%

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A CMOS W-Band Amplifier with Tunable Neutralization Using a Cross-Coupled MOS–varactor Pair

Yook

Park

et al. 2019

Electronics

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This paper presents a CMOS W-band amplifier adopting a novel neutralization technique for high gain and stability. The W-band amplifier consists of four common-source differential gain cells that are neutralized by a cross-coupled MOS–varactor pair. Contrary to conventional neutralizations, the proposed technique enables tunable neutralization, so that the gate-to-drain capacitance of transistors is accurately tracked and neutralized as the varactor voltage is adjusted. This makes the neutralization tolerant of capacitance change caused by process–voltage–temperature (PVT) variation or transistor model inaccuracy, which commonly occurs at mm-wave frequencies. The proposed tunable neutralization is experimentally confirmed by measuring gain and stability of the W-band amplifier fabricated in a 65-nm CMOS process. The amplifier achieves a measured gain of 17.5 dB at 79 GHz and a 3-dB bandwidth from 77.5 to 84 GHz without any stability issue. The DC power consumption is 56.7 mW and the chip area is 0.85 mm2.

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